View OR3T55_929068.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

data sheet june 1999 orca ? series 3c and 3t field-programmable gate arrays features n high-performance, cost-effective, 0.35 m (or3c) and 0.3 m (or3t) 4-level metal technology, (4- or 5-input look-up table delay of 1.1 ns with -7 speed grade in 0.3 m). n same basic architecture as lower-voltage, advanced process technology series 3 architectures. (see orca series 3l fpga documentation.) n up to 186,000 usable gates. n up to 452 user i/os. (or3txxx i/os are 5 v tolerant to allow interconnection to both 3.3 v and 5 v devices, selectable on a per-pin basis.) n pin selectable i/o clamping diodes provide 5 v or 3.3 v pci compliance and 5 v tolerance on or3txxx devices. n twin-quad programmable function unit (pfu) architec- ture with eight 16-bit look-up tables (luts) per pfu, organized in two nibbles for use in nibble- or byte-wide functions. allows for mixed arithmetic and logic functions in a single pfu. n nine user registers per pfu, one following each lut, plus one extra. all have programmable clock enable and local set/reset, plus a global set/reset that can be dis- abled per pfu. n flexible input structure (fins) of the pfus provides a routability enhancement for luts with shared inputs and the logic flexibility of luts with independent inputs. n fast-carry logic and routing to adjacent pfus for nibble-, byte-wide, or longer arithmetic functions, with the option to register the pfu carry-out. n softwired luts (swl) allow fast cascading of up to three levels of lut logic in a single pfu for up to 40% speed improvement. n supplemental logic and interconnect cell (slic) provides 3-statable buffers, up to 10-bit decoder, and pa l *-like and-or with optional invert in each programmable logic cell (plc), with over 50% speed improvement typi- cal. n abundant hierarchical routing resources based on rout- ing two data nibbles and two control lines per set provide for faster place and route implementations and less rout- ing delay. n ttl or cmos input levels programmable per pin for the or3cxx (5.0 v) devices. n individually programmable drive capability: 12 ma sink/6 ma source or 6 ma sink/3 ma source. n built-in boundary scan ( ieee ? 1149.1 jtag) and ts_all testability function to 3-state all i/o pins. n enhanced system clock routing for low skew, high-speed clocks originating on-chip or at any i/o. n up to four expressclk inputs allow extremely fast clock- ing of signals on- and off-chip plus access to internal general clock routing. n stopclk feature to glitchlessly stop/start expressclks independently by user command. n programmable i/o (pio) has: fast-capture input latch and input flip-flop (ff) latch for reduced input setup time and zero hold time. capability to (de)multiplex i/o signals. fast access to slic for decodes and pa l -like functions. output ff and two-signal function generator to reduce clk to output propagation delay. fast open-drain dive capability capability to register 3-state enable signal. n baseline fpga family used in series 3+ fpscs (field programmable system chips) which combine fpga logic and standard cell logic on one device. * pa l is a trademark of advanced micro devices, inc. ? ieee is a registered trademark of the institute of electrical and electronics engineers, inc. table 1. orca series 3 (3c and 3t) fpgas ? the system gate counts range from a logic-only gate count to a gate count assuming 30% of the pfus/slics being used as rams. the logic-only gate count includes each pfu/slic (counted as 108 gates per pfu/slic), including 12 gates per lut/ff pair (eight per pfu), and 12 gates per slic/ff pair (one per pfu). each of the four pios per pic is counted as 16 gates (two ffs, fast-capture latch, output logic, clk drivers, and i/o buffers). pfus used as ram are counted at four gates per bit, with each pfu capable of imple menting a 32 x 4 ram (or 512 gates) per pfu. device system gates ? luts registers max user ram user i/os array size process technology or3t20 36k 1152 1872 18k 196 12 x 12 0.3 m/4 lm or3t30 48k 1568 2436 25k 228 14 x 14 0.3 m/4 lm or3c/3t55 80k 2592 3780 42k 292 18 x 18 0.3 m/4 lm or3c/3t80 116k 3872 5412 62k 356 22 x 22 0.3 m/4 lm or3t125 186k 6272 8400 100k 452 28 x 28 0.3 m/4 lm
table of contents contents page contents page 2 lucent technologies inc. data sheet june 1999 orca series 3c and 3t fpgas features ......................................................................1 system-level features................................................6 description...................................................................7 fpga overview ........................................................7 plc logic ..................................................................7 pic logic ...................................................................8 system features .......................................................8 routing ......................................................................8 configuration .............................................................8 orca foundry development system ......................9 architecture .................................................................9 programmable logic cells ........................................11 programmable function unit ..................................11 look-up table operating modes ............................13 supplemental logic and interconnect cell (slic) ..21 plc latches/flip-flops ...........................................25 plc routing resources ..........................................27 plc architectural description .................................34 programmable input/output cells .............................36 5 v tolerant i/o .......................................................37 pci compliant i/o ...................................................37 inputs ......................................................................38 outputs ....................................................................41 pic routing resources ...........................................44 pic architectural description ..................................45 high-level routing resources..................................47 interquad routing ....................................................47 programmable corner cell routing ........................48 pic interquad (mid) routing ...................................49 clock distribution network ........................................50 pfu clock sources .................................................50 clock distribution in the plc array .........................51 clock sources to the plc array .............................52 clocks in the pics ...................................................52 expressclk inputs .................................................53 selecting clock input pins ......................................53 special function blocks ............................................54 single function blocks ............................................54 boundary scan ........................................................57 microprocessor interface (mpi) .................................64 powerpc system ....................................................65 i960 system ............................................................66 mpi interface to fpga ............................................67 mpi setup and control ............................................68 programmable clock manager (pcm) ......................72 pcm registers ........................................................73 delay-locked loop (dll) mode .............................75 phase-locked loop (pll) mode ............................76 pcm/fpga internal interface .................................79 pcm operation .......................................................79 pcm detailed programming ...................................80 pcm applications ....................................................83 pcm cautions ........................................................ 84 fpga states of operation........................................ 85 initialization ............................................................. 85 configuration .......................................................... 86 start-up .................................................................. 87 reconfiguration ...................................................... 88 partial reconfiguration ........................................... 88 other configuration options ................................... 88 configuration data format ...................................... 89 using orca foundry to generate configuration ram data ....................................... 89 configuration data frame ...................................... 89 bit stream error checking ...................................... 91 fpga configuration modes...................................... 92 master parallel mode ............................................. 92 master serial mode ................................................ 93 asynchronous peripheral mode ............................. 94 microprocessor interface (mpi) mode .................... 94 slave serial mode .................................................. 97 slave parallel mode ............................................... 97 daisy-chaining ....................................................... 98 daisy-chaining with boundary scan ...................... 99 absolute maximum ratings.................................... 100 recommended operating conditions .................. 100 electrical characteristics ........................................ 101 timing characteristics ............................................ 103 description ........................................................... 103 pfu timing ......................................................... 104 plc timing ........................................................... 111 slic timing .......................................................... 111 pio timing ........................................................... 112 special function blocks timing ........................... 115 clock timing ......................................................... 123 configuration timing ............................................ 133 readback timing ................................................. 142 input/output buffer measurement conditions ........ 143 output buffer characteristics ................................. 144 or3cxx ................................................................ 144 or3txxx .............................................................. 145 estimating power dissipation ................................. 146 or3cxx ................................................................ 146 or3txxx (preliminary information) ...................... 147 pin information ....................................................... 149 pin descriptions ................................................... 149 package compatibility .......................................... 153 compatibility with or2c/txxa series .................. 154 package thermal characteristics........................... 194 q ja ....................................................................... 194 y jc ...................................................................... 194 q jc ...................................................................... 194 q jb ...................................................................... 194 fpga maximum junction temperature ............... 195
table of contents contents page contents page lucent technologies inc. 3 orca series 3c and 3t fpgas june 1999 data sheet package coplanarity ...............................................196 package parasitics ..................................................196 package outline diagrams......................................197 terms and definitions ...........................................197 208-pin sqfp .......................................................198 208-pin sqfp2 .....................................................199 240-pin sqfp .......................................................200 240-pin sqfp2 .....................................................201 256-pin pbga .......................................................202 352-pin pbga .......................................................203 432-pin ebga .......................................................204 600-pin ebga .......................................................205 ordering information................................................206 index........................................................................207 tables table 1. orca series 3 (3c and 3t) fpgas ............ 2 table 2. orca series 3 system performance .......... 6 table 3. look-up table operating modes ............... 13 table 4. control input functionality .......................... 14 table 5. ripple mode equality comparator functions and outputs ............................................ 18 table 6. slic modes ................................................ 21 table 7. configuration ram controlled latch/flip-flop operation ........................................ 25 table 8. inter-plc routing resources ..................... 31 table 9. pio options ................................................ 37 table 10. pio logic options .................................... 43 table 11. pio register control signals .................... 43 table 12. readback options .................................... 54 table 13. boundary-scan instructions ..................... 58 table 14. boundary-scan id code ........................... 59 table 15. tap controller input/outputs ................... 61 table 16. powerpc /mpi configuration ..................... 65 table 17. i960 /mpi configuration ............................. 66 table 18. mpi internal interface signals .................. 67 table 19. mpi setup and control registers ............. 68 table 20. mpi setup and control registers description ............................................................... 68 table 21. mpi control register 2 ............................. 69 table 22. status register ......................................... 70 table 23. device id code ........................................ 71 table 24. series 3 family and device id values ..... 71 table 25. orca series 3 device id descriptions .... 71 table 26. pcm registers ......................................... 73 table 27. dll mode delay/1x duty cycle programming values ............................................... 75 table 28. dll mode delay/2x duty cycle programming values ............................................... 76 table 29. pcm oscillator frequency range 3txxx . 78 table 30. pcm oscillator frequency range 3cxx ... 78 table 31. pcm control registers ............................. 80 table 32. configuration frame format and contents ..................................................................90 table 33. configuration frame size .........................91 table 34. configuration modes ................................92 table 35. absolute maximum ratings ....................100 table 36. recommended operating conditions ....100 table 37. electrical characteristics ........................101 table 38. derating for commercial devices (or3cxx) ..............................................................103 table 39. derating for industrial devices (or3cxx) 103 table 40. derating for commercial/industrial devices (or3txxx) ...............................................103 table 41. combinatorial pfu timing characteristics .......................................................104 table 42. sequential pfu timing characteristics ..106 table 43. ripple mode pfu timing characteristics .......................................................107 table 44. synchronous memory write characteristics .......................................................109 table 45. synchronous memory read characteristics .......................................................110 table 46. pfu output mux and direct routing timing characteristics ...........................................111 table 47. supplemental logic and interconnect cell (slic) timing characteristics ........................111 table 48. programmable i/o (pio) timing characteristics .......................................................112 table 49. microprocessor interface (mpi) timing characteristics .......................................................115 table 50. programmable clock manager (pcm) timing characteristics (preliminary information) ..121 table 51. boundary-scan timing characteristics ..122 table 52. expressclk (eclk) and fast clock (fclk) timing characteristics ..............................123 table 53. general-purpose clock timing characteristics (internally generated clock) .........124 table 54. or3cxx expressclk to output delay (pin-to-pin) ............................................................125 table 55. or3cxx fast clock (fclk) to output delay (pin-to-pin) ..................................................126 table 56. or3cxx general system clock (sclk) to output delay (pin-to-pin) ..................................127 table 57. or3c/txxx input to expressclk (eclk) fast-capture setup/hold time (pin-to-pin) ..........128 table 58. or3c/txxx input to fast clock setup/hold time (pin-to-pin) ................................130 table 59. or3c/txxx input to general system clock (sclk) setup/hold time (pin-to-pin) ..........132 table 60. general configuration mode timing characteristics .......................................................133 table 61. master serial configuration mode timing
table of contents contents page contents page 4 lucent technologies inc. data sheet june 1999 orca series 3c and 3t fpgas characteristics ...................................................... 136 table 62. master parallel configuration mode timing characteristics ...................................................... 137 table 63. asynchronous peripheral configuration mode timing characteristics ........................................... 138 table 64. slave serial configuration mode timing characteristics ...................................................... 139 table 65. slave parallel configuration mode timing characteristics ........................................... 140 table 66. readback timing characteristics ........... 142 table 67. pin descriptions ...................................... 149 table 68. orca i/os summary ............................. 153 table 69. series 3 expressclk pins ..................... 154 table 70. or3t20, or3t30, or3c/t55, or3c/t80, and or3t125 208-pin sqfp/sqfp2 pinout ............................................ 155 table 71. or3t20, or3t30, or3c/t55, or3c/t80, and or3t125 240-pin sqfp/sqfp2 pinout ............................................ 161 table 72. or3t20, or3t30, and or3c/t55 256-pin pbga pinout ............................................ 168 table 73. or3t20, or3t30, or3c/t55, or3c/t80, and or3t125 352-pin pbga pinout . 172 table 74. or3c/t80 and or3t125 432-pin ebga pinout ......................................................... 182 table 75. or3t125 600-pin ebga pinout ............ 187 table 76. plastic package thermal characteristics for the orca series ..................... 195 table 77. package coplanarity .............................. 196 table 78. package parasitics ................................. 196 table 79. voltage options ...................................... 206 table 80. temperature options ............................. 206 table 81. package options .................................... 206 table 82. orca series 3 package matrix ............. 206 table 83. speed grade options ............................. 206 figures figure 1. or3c/t55 array ........................................ 10 figure 2. pfu ports .................................................. 11 figure 3. simplified pfu diagram ............................ 12 figure 4. simplified f4 and f5 logic modes ............ 14 figure 5. softwired lut topology examples ........... 15 figure 6. ripple mode .............................................. 16 figure 7. counter submode ..................................... 17 figure 8. multiplier submode .................................... 18 figure 9. memory mode ........................................... 19 figure 10. memory mode expansion example 128 x 8 ram ........................................................... 20 figure 11. slic all modes diagram ......................... 22 figure 12. buffer mode ............................................. 22 figure 13. buffer-buffer-decoder mode ................... 23 figure 14. buffer-decoder-buffer mode ...................23 figure 15. buffer-decoder-decoder mode ...............24 figure 16. decoder mode .........................................24 figure 17. latch/ff set/reset configurations .........26 figure 18. configurable interconnect point ..............27 figure 19. single plc view of inter-plc route segments ................................................................28 figure 20. multiple plc view of inter-plc routing .32 figure 21. plc architecture .....................................35 figure 22. or3c/txxx programmable input/output (pio) image from orca foundry ...........................36 figure 23. fast-capture latch and timing ...............39 figure 24. pio input demultiplexing .........................40 figure 25. output multiplexing (out1out2 mode) .42 figure 26. output multiplexing (out2outreg mode) ...........................................42 figure 27. pic architecture ......................................46 figure 28. interquad routing ....................................47 figure 29. hiq block detail .......................................48 figure 30. top (tmid) routing .................................49 figure 31. pfu clock sources .................................50 figure 32. orca series 3 system clock distribution overview ..............................................51 figure 33. pic system clock spine generation ......52 figure 34. expressclk and fast clock distribution 53 figure 35. top clkcntrl function block ..............56 figure 36. printed-circuit board with boundary- scan circuitry ..........................................................57 figure 37. boundary-scan interface .........................58 figure 38. orca series boundary-scan circuitry functional diagram .................................................60 figure 39. tap controller state transition diagram 61 figure 40. boundary-scan cell ................................62 figure 41. instruction register scan timing diagram ...................................................................63 figure 42. mpi block diagram ..................................64 figure 43. powerpc /mpi ..........................................65 figure 44. i960 /mpi ..................................................66 figure 45. pcm block diagram ................................72 figure 46. pcm functional block diagram ..............74 figure 47. expressclk delay minimization using the pcm ..................................................................76 figure 48. clock phase adjustment using the pcm 83 figure 49. fpga states of operation .......................85 figure 50. initialization/configuration/start-up waveforms ..............................................................86 figure 51. start-up waveforms ................................88 figure 52. serial configuration data format autoincrement mode ...............................................90 figure 53. serial configuration data format
table of contents contents page contents page lucent technologies inc. 5 orca series 3c and 3t fpgas june 1999 data sheet explicit mode ........................................................... 90 figure 54. master parallel configuration schematic 92 figure 55. master serial configuration schematic ... 93 figure 56. asynchronous peripheral configuration .. 94 figure 57. powerpc /mpi configuration schematic .. 95 figure 58. i960 /mpi configuration schematic .......... 95 figure 59. configuration through mpi ..................... 95 figure 60. readback through mpi .......................... 96 figure 61. slave serial configuration schematic ..... 97 figure 62. slave parallel configuration schematic .. 97 figure 63. daisy-chain configuration schematic ..... 98 figure 64. combinatorial pfu timing .................... 105 figure 65. synchronous memory write characteristics ...................................................... 109 figure 66. synchronous memory read cycle ........ 110 figure 67. mpi powerpc user space read timing 117 figure 68. mpi powerpc user space write timing 117 figure 69. mpi powerpc internal read timing ..... 118 figure 70. mpi powerpc internal write timing ...... 118 figure 71. mpi i960 user space read timing ....... 119 figure 72. mpi i960 user space write timing ....... 119 figure 73. mpi i960 internal read timing .............. 120 figure 74. mpi i960 internal write timing .............. 120 figure 75. boundary-scan timing diagram ........... 122 figure 76. expressclk to output delay ................ 125 figure 77. fast clock to output delay ................... 126 figure 78. system clock to output delay .............. 127 figure 79. input to expressclk setup/hold time .. 129 figure 80. input to fast clock setup/hold time ..... 131 figure 81. input to system clock setup/hold time 132 figure 82. general configuration mode timing diagram .................................................................135 figure 83. master serial configuration mode timing diagram .....................................................136 figure 84. master parallel configuration mode timing diagram .....................................................137 figure 85. asynchronous peripheral configuration mode timing diagram ...........................................138 figure 86. slave serial configuration mode timing diagram .....................................................139 figure 87. slave parallel configuration mode timing diagram .....................................................140 figure 88. readback timing diagram ....................142 figure 89. ac test loads ........................................143 figure 90. output buffer delays .............................143 figure 91. input buffer delays ................................143 figure 92. sinklim (t j = 25 c, v dd = 5.0 v) ..........144 figure 93. slewlim (t j = 25 c, v dd = 5.0 v) .........144 figure 94. fast (t j c, v dd = 5.0 v) ......................144 figure 95. sinklim (t j = 125 c, v dd = 4.5 v) ........144 figure 96. slewlim (t j = 125 c, v dd = 4.5 v) .......144 figure 97. fast (t j = 125 c, v dd = 4.5 v) ............144 figure 98. sinklim (t j = 25 c, v dd = 3.3 v) ..........145 figure 99. slewlim (t j = 25 c, v dd = 3.3 v) .........145 figure 100. fast (t j = 25 c, v dd = 3.3 v) ............145 figure 101. sinklim (t j = 125 c, v dd = 3.0 v) ......145 figure 102. slewlim (t j = 125 c, v dd = 3.0 v) .....145 figure 103. fast (t j = 125 c, v dd = 3.0 v) ..........145 figure 104. package parasitics ..............................196
6 6 lucent technologies inc. data sheet june 1999 orca series 3c and 3t fpgas system-level features system-level features reduce glue logic requirements and make a system on a chip possible. these features in the orca series 3 include: n full pci local bus compliance. n dual-use microprocessor interface (mpi) can be used for configuration, readback, device control, and device status, as well as for a general-purpose inter- face to the fpga. glueless interface to i960 * and powerpc ? processors with user-configurable address space provided. n parallel readback of configuration data capability with the built-in microprocessor interface. n programmable clock manager (pcm) adjusts clock phase and duty cycle for input clock rates from 5 mhz to 120 mhz. the pcm may be combined with fpga logic to create complex functions, such as dig- ital phase-locked loops (dpll), frequency counters, and frequency synthesizers or clock doublers. two pcms are provided per device. n true, internal, 3-state, bidirectional buses with simple control provided by the slic. n 32 x 4 ram per pfu, configurable as single- or dual- port at >176 mhz. create large, fast ram/rom blocks (128 x 8 in only eight pfus) using the slic decoders as bank drivers. * i960 is a registered trademark of intel corporation. ? powerpc is a registered trademark of international business machines corporation. table 2. orca series 3 system performance 1. implemented using 8 x 1 multiplier mode (unpipelined), register-to-register, two 8-bit inputs, one 16-bit output. 2. implemented using two 32 x 12 roms and one 12-bit adder, one 8-bit input, one fixed operand, one 16-bit output. 3. implemented using 8 x 1 multiplier mode (fully pipelined), two 8-bit inputs, one 16-bit output (7 of 15 pfus contain only pi pelining registers). 4. implemented using 32 x 4 ram mode with read data on 3-state buffer to bidirectional read/write bus. 5. implemented using 32 x 4 dual-port ram mode. 6. implemented in one partially occupied slic with decoded output set up to ce in same plc. 7. implemented in five partially occupied slics. parameter # pfus speed unit -4 -5 -6 -7 16-bit loadable up/down counter 2 78 102 131 168 mhz 16-bit accumulator 2 78 102 131 168 mhz 8 x 8 parallel multiplier: multiplier mode, unpipelined 1 rom mode, unpipelined 2 multiplier mode, pipelined 3 11.5 8 15 19 51 76 25 66 104 30 80 127 38 102 166 mhz mhz mhz 32 x 16 ram (synchronous): single-port, 3-state bus 4 dual-port 5 4 4 97 127 127 166 151 203 192 253 mhz mhz 128 x 8 ram (synchronous): single-port, 3-state bus 4 dual-port 5 8 8 88 88 116 116 139 139 176 176 mhz mhz 8-bit address decode (internal): using softwired luts using slics 6 0.25 0 4.87 2.35 3.66 1.82 2.58 1.23 2.03 0.99 ns ns 32-bit address decode (internal): using softwired luts using slics 7 2 0 16.06 6.91 12.07 5.41 9.01 4.21 7.03 3.37 ns ns 36-bit parity check (internal) 2 16.06 12.07 9.01 7.03 ns
lucent technologies inc. 7 data sheet june 1999 orca series 3c and 3t fpgas description fpga overview the orca series 3 fpgas are a new generation of sram-based fpgas built on the successful or2c/ txxa fpga series from lucent technologies micro- electronics group, with enhancements and innovations geared toward todays high-speed designs and tomor- rows systems on a single chip. designed from the start to be synthesis friendly and to reduce place and route times while maintaining the complete routability of the orca 2c/2t devices, series 3 more than doubles the logic available in each logic block and incorporates sys- tem-level features that can further reduce logic require- ments and increase system speed. orca series 3 devices contain many new patented enhancements and are offered in a variety of packages, speed grades, and temperature ranges. the orca series 3 fpgas consist of three basic ele- ments: programmable logic cells (plcs), programma- ble input/output cells (pics), and system-level features. an array of plcs is surrounded by pics. each plc contains a programmable function unit (pfu), a sup- plemental logic and interconnect cell (slic), local rout- ing resources, and configuration ram. most of the fpga logic is performed in the pfu, but decoders, pa l -like functions, and 3-state buffering can be per- formed in the slic. the pics provide device inputs and outputs and can be used to register signals and to perform input demultiplexing, output multiplexing, and other functions on two output signals. some of the sys- tem-level functions include the new microprocessor interface ( mpi ) and the programmable clock manager ( pcm ). plc logic each pfu within a plc contains eight 4-input (16-bit) look-up tables (luts), eight latches/flip-flops (ffs), and one additional flip-flop that may be used indepen- dently or with arithmetic functions. the pfu is organized in a twin-quad fashion: two sets of four luts and ffs that can be controlled indepen- dently. luts may also be combined for use in arith- metic functions using fast-carry chain logic in either 4-bit or 8-bit modes. the carry-out of either mode may be registered in the ninth ff for pipelining. each pfu may also be configured as a synchronous 32 x 4 sin- gle- or dual-port ram or rom. the ffs (or latches) may obtain input from lut outputs or directly from invertible pfu inputs, or they can be tied high or tied low. the ffs also have programmable clock polarity, clock enables, and local set/reset. the slic is connected to plc routing resources and to the outputs of the pfu. it contains 3-state, bidirectional buffers and logic to perform up to a 10-bit and function for decoding, or an and-or with optional invert (aoi) to perform pa l -like functions. the 3-state drivers in the slic and their direct connections to the pfu out- puts make fast, true 3-state buses possible within the fpga, reducing required routing and allowing for real- world system performance.
8 8 lucent technologies inc. data sheet june 1999 orca series 3c and 3t fpgas description (continued) pic logic series 3 pic addresses the demand for ever-increas- ing system clock speeds. each pic contains four pro- grammable inputs/outputs (pios) and routing resources. on the input side, each pio contains a fast- capture latch that is clocked by an expressclk. this latch is followed by a latch/ff that is clocked by a sys- tem clock from the internal general clock routing. the combination provides for very low setup requirements and zero hold times for signals coming on-chip. it may also be used to demultiplex an input signal, such as a multiplexed address/data signal, and register the sig- nals without explicitly building a demultiplexer. two input signals are available to the plc array from each pio, and the orca 2c/2t capability to use any input pin as a clock or other global input is maintained. on the output side of each pio, two outputs from the plc array can be routed to each output flip-flop, and logic can be associated with each i/o pad. the output logic associated with each pad allows for multiplexing of output signals and other functions of two output sig- nals. the output ff in combination with output signal multi- plexing, is particularly useful for registering address signals to be multiplexed with data, allowing a full clock cycle for the data to propagate to the output. the i/o buffer associated with each pad is very similar to the orca 2c/2t series buffer with a new, fast, open-drain option for ease of use on system buses. system features series 3 also provides system-level functionality by means of its dual-use microprocessor interface and its innovative programmable clock manager. these func- tional blocks allow for easy glueless system interfacing and the capability to adjust to varying conditions in todays high-speed systems. routing the abundant routing resources of the orca series 3 fpgas are organized to route signals individually or as buses with related control signals. clocks are routed on a low-skew, high-speed distribution network and may be sourced from plc logic, externally from any i/o pad, or from the very fast expressclk pins. express- clks may be glitchlessly and independently enabled and disabled with a programmable control signal using the new stopclk feature. the improved pic routing resources are now similar to the patented intra-plc routing resources and provide great flexibility in moving signals to and from the pios. this flexibility translates into an improved capability to route designs at the required speeds when the i/o signals have been locked to specific pins. configuration the fpgas functionality is determined by internal configuration ram. the fpgas internal initialization/ configuration circuitry loads the configuration data at powerup or under system control. the ram is loaded by using one of several configuration modes. the con- figuration data resides externally in an eeprom or any other storage media. serial eeproms provide a sim- ple, low pin count method for configuring fpgas. a new, easy method for configuring the devices is through the microprocessor interface.
lucent technologies inc. 9 data sheet june 1999 orca series 3c and 3t fpgas description (continued) orca foundry development system the orca foundry development system is used to process a design from a netlist to a configured fpga. this system is used to map a design onto the orca architecture and then place and route it using orca foundrys timing-driven tools. the development system also includes interfaces to, and libraries for, other popu- lar cae tools for design entry, synthesis, simulation, and timing analysis. the orca foundry development system interfaces to front-end design entry tools and provides the tools to produce a configured fpga. in the design flow, the user defines the functionality of the fpga at two points in the design flow: at design entry and at the bit stream generation stage. following design entry, the development systems map, place, and route tools translate the netlist into a routed fpga. a static timing analysis tool is provided to deter- mine device speed and a back-annotated netlist can be created to allow simulation. timing and simulation out- put files from orca foundry are also compatible with many third-party analysis tools. its bit stream generator is then used to generate the configuration data which is loaded into the fpgas internal configuration ram. when using the bit stream generator, the user selects options that affect the functionality of the fpga. com- bined with the front-end tools, orca foundry pro- duces configuration data that implements the various logic and routing options discussed in this data sheet. architecture the orca series 3 fpga comprises three basic ele- ments: plcs, pics, and system-level functions. figure 1 shows an array of programmable logic cells (plcs) surrounded by programmable input/output cells (pics). also shown are the interquad routing blocks (hiq, viq) present in series 3. system-level functions (located in the corners of the array) and the routing resources and configuration ram are not shown in figure 1. the or3c/t55 array in figure 1 has plcs arranged in an array of 18 rows and 18 columns. the location of a plc is indicated by its row and column so that a plc in the second row and the third column is r2c3. pics are located on all four sides of the fpga between the plcs and the device edge. pics are indicated using pt and pb to designate pics on the top and bottom sides of the array, respectively, and pl and pr to des- ignate pics along the left and right sides of the array, respectively. the position of a pic on an edge of the array is indicated by a number, counting from left to right for pt and pb and top to bottom for pl and pr pics. each pic contains routing resources and four program- mable i/os (pios). each pio contains the necessary i/o buffers to interface to bond pads. pios in series 3 fpgas also contain input and output ffs, fast open- drain capability on output buffers, special output logic functions, and signal multiplexing/demultiplexing capa- bilities. plcs comprise a programmable function unit (pfu), a supplemental logic and interconnect cell (slic), and routing resources. the pfu is the main logic element of the plc, containing elements for both combinatorial and sequential logic. combinatorial logic is done in look-up tables (luts) located in the pfu. the pfu can be used in different modes to meet different logic requirements. the luts twin-quad architecture pro- vides a configurable medium-/large-grain architecture that can be used to implement from one to eight inde- pendent combinatorial logic functions or a large num- ber of complex logic functions using multiple luts. the flexibility of the lut to handle wide input functions, as well as multiple smaller input functions, maximizes the gate count per pfu while increasing system speed. the luts can be programmed to operate in one of three modes: combinatorial, ripple, or memory. in com- binatorial mode, the luts can realize any 4- or 5-input logic function and many multilevel logic functions using orca s softwired lut ( swl ) connections. in ripple mode, the high-speed carry logic is used for arithmetic functions, comparator functions, or enhanced data path functions. in memory mode, the luts can be used as a 32 x 4 synchronous read/write or read-only memory, in either single- or dual-port mode.
10 lucent technologies inc. data sheet june 1999 orca series 3c and 3t fpgas architecture (continued) 5-4489(f) figure 1. or3c/t55 array vi pl9 pl8 pl7 pl6 pl5 pl4 pl3 pl2 pl1 pl13 pl12 pl11 pr12 pr11 pr9 pr8 pr7 pr6 pr5 pr4 pr3 pr2 pr1 pr13 pr18 pr17 pr16 pr15 pr14 rmid pr10 pt1 pt2 pt3 pt4 pt5 pt6 pt7 pt8 pt9 pt11 pt12 r1c1 r1c2 r1c3 r1c4 r1c5 r1c6 r1c7 r1c8 r1c9 r1c10 r1c18 r1c17 r1c16 r1c15 r1c14 r1c13 r1c12 r1c11 pt13 pt14 pt15 pt16 pt17 pt18 pb1 pb2 pb3 pb4 pb5 pb6 pb7 pb8 pb9 pb10 pb11 pb12 pl18 pl17 pl16 pl15 pl14 pb13 pb14 pb15 pb16 pb17 pb18 pl10 bmid pt10 viq r2c1 r2c2 r2c3 r2c4 r2c5 r2c6 r2c7 r2c8 r2c9 r2c10 r3c1 r3c2 r3c3 r3c4 r3c5 r3c6 r3c7 r3c8 r3c9 r3c10 r4c1 r4c2 r4c3 r4c4 r4c5 r4c6 r4c7 r4c8 r4c9 r4c10 r5c1 r5c2 r5c3 r5c4 r5c5 r5c6 r5c7 r5c8 r5c9 r5c10 r6c1 r6c2 r6c3 r6c4 r6c5 r6c6 r6c7 r6c8 r6c9 r6c10 r7c1 r7c2 r7c3 r7c4 r7c5 r7c6 r7c7 r7c8 r7c9 r7c10 r8c1 r8c2 r8c3 r8c4 r8c5 r8c6 r8c7 r8c8 r8c9 r8c10 r9c1 r9c2 r9c3 r9c4 r9c5 r9c6 r9c7 r9c8 r9c9 r9c10 r10c1 r10c2 r10c3 r10c4 r10c5 r10c6 r10c7 r10c8 r10c9 r10c10 r2c18 r2c17 r2c16 r2c15 r2c14 r2c13 r2c12 r2c11 r3c18 r3c17 r13c16 r3c15 r3c14 r3c13 r3c12 r3c11 r4c18 r4c17 r4c16 r4c15 r4c14 r4c13 r4c12 r4c11 r5c18 r5c17 r5c16 r5c15 r5c14 r5c13 r5c12 r5c11 r6c18 r6c17 r6c16 r6c15 r6c14 r6c13 r6c12 r6c11 r7c18 r7c17 r7c16 r7c15 r7c14 r7c13 r7c12 r7c11 r8c18 r8c17 r8c16 r8c15 r8c14 r8c13 r8c12 r8c11 r9c18 r9c17 r9c16 r9c15 r9c14 r9c13 r9c12 r9c11 r10c18 r10c17 r10c16 r10c15 r10c14 r10c13 r10c12 r10c11 r18c18 r18c17 r18c16 r18c15 r18c14 r18c13 r18c12 r18c11 r17c18 r17c17 r17c16 r17c15 r17c14 r17c13 r17c12 r17c11 r16c18 r16c17 r16c16 r16c15 r16c14 r16c13 r16c12 r16c11 r15c18 r15c17 r15c16 r15c15 r15c14 r15c13 r15c12 r15c11 r14c18 r14c17 r14c16 r14c15 r14c14 r14c13 r14c12 r14c11 r13c18 r13c17 r13c16 r13c15 r13c14 r13c13 r13c12 r13c11 r12c18 r12c17 r12c16 r12c15 r12c14 r12c13 r12c12 r12c11 r11c18 r11c17 r11c16 r11c15 r11c14 r11c13 r11c12 r11c11 r18c10 r18c9 r18c8 r18c7 r18c6 r18c5 r18c4 r18c3 r18c2 r18c1 r17c10 r17c9 r17c8 r17c7 r17c6 r17c5 r17c4 r17c3 r17c2 r17c1 r16c10 r16c9 r16c8 r16c7 r16c6 r16c5 r16c4 r16c3 r16c2 r16c1 r15c10 r15c9 r15c8 r15c7 r15c6 r15c5 r15c4 r15c3 r15c2 r15c1 r14c10 r14c9 r14c8 r14c7 r14c6 r14c5 r14c4 r14c3 r14c2 r14c1 r13c10 r13c9 r13c8 r13c7 r13c6 r13c5 r13c4 r13c3 r13c2 r13c1 r12c10 r12c9 r12c8 r12c7 r12c6 r12c5 r12c4 r12c3 r12c2 r12c1 r11c10 r11c9 r11c8 r11c7 r11c6 r11c5 r11c4 r11c3 r11c2 r11c1 hiq tmid lmid
lucent technologies inc. 11 data sheet june 1999 orca series 3c and 3t fpgas programmable logic cells the programmable logic cell (plc) consists of a pro- grammable function unit (pfu), a supplemental logic and interconnect cell (slic), and routing resources. all plcs in the array are functionally identical with only minor differences in routing connectivity for improved routability. the pfu, which contains eight 4-input luts, eight latches/ffs, and one ff for logic implementation, is discussed in the next section, followed by discus- sions of the slic and plc routing resources. programmable function unit the pfus are used for logic. each pfu has 50 external inputs and 18 outputs and can operate in several modes. the functionality of the inputs and outputs depends on the operating mode. the pfu uses 36 data input lines for the luts, eight data input lines for the latches/ffs, five control inputs (aswe, clk, ce, lsr, sel), and a carry input (cin) for fast arithmetic functions and general-purpose data input for the ninth ff. there are eight combinatorial data outputs (one from each lut), eight latched/registered outputs (one from each latch/ff), a carry-out (cout), and a registered carry-out (regcout) that comes from the ninth ff. the carry-out signals are used principally for fast arithmetic functions. figure 2 and figure 3 show high-level and detailed views of the ports in the pfu, respectively. the eight sets of lut inputs are labeled as k 0 through k 7 with each of the four inputs to each lut having a suffix of _x, where x is a number from 0 to 3. there are four f5 inputs labeled a through d. these inputs are used for a fifth lut input for 5-input luts or as a selector for multi- plexing two 4-input luts. the eight direct data inputs to the latches/ffs are labeled as din[7:0]. registered lut outputs are shown as q [7:0] , and combinatorial lut outputs are labeled as f [7:0] . the pfu implements combinatorial logic in the luts and sequential logic in the latches/ffs. the luts are static random access memory (sram) and can be used for read/write or read-only memory. each latch/ff can accept data from its associated lut. alternatively, the latches/ffs can accept direct data from din[7:0], eliminating the lut delay if no combina- torial function is needed. additionally, the cin input can be used as a direct data source for the ninth ff. the lut outputs can bypass the latches/ffs, which reduces the delay out of the pfu. it is possible to use the luts and latches/ffs more or less independently, allowing, for instance, a comparator function in the luts simulta- neously with a shift register in the ffs. 5-5752(f) figure 2. pfu ports the pfu can be configured to operate in four modes: logic mode, half-logic mode, ripple mode, and memory (ram/rom) mode. in addition, ripple mode has four submodes and ram mode can be used in either a single- or dual-port memory fashion. these submodes of operation are discussed in the following sections. 5-5752(f) f5d k 7 _0 k 7 _1 k 7 _2 k 7 _3 k 6 _0 k 6 _1 k 6 _2 k 6 _3 k 5 _0 k 5 _1 k 5 _2 k 5 _3 k 4 _0 k 4 _1 k 4 _2 k 4 _3 f5c din7 din6 din5 din4 din3 din2 din1 din0 cin f5b k 3 _0 k 3 _1 k 3 _2 k 3 _3 k 2 _0 k 2 _1 k 2 _2 k 2 _3 k 1 _0 k 1 _1 k 1 _2 k 1 _3 k 0 _0 k 0 _1 k 0 _2 k 0 _3 f5a lsr clk ce sel aswe programmable function unit (pfu) q7 q6 q5 q4 q3 q2 q1 q0 cout regcout f7 f6 f5 f4 f3 f2 f1 f0
12 lucent technologies inc. data sheet june 1999 orca series 3c and 3t fpgas programmable logic cells (continued) 5-5743(f) note: all multiplexers without select inputs are configuration selector multiplexers. figure 3. simplified pfu diagram sel cin d ce ck s/r ff8 regcout cout 1 aswe lsr k7_3 k6_0 k6_1 k6_2 k6_3 k5_0 k5_1 k5_2 f5d k7_0 k7_1 k7_2 k5_3 k4_0 k4_1 k4_2 k4_3 f5c clk a b c d a b c d a b c d k4 k5 k6 k7 din7 din6 din5 din4 reg5 d0 d1 ce ck s/r dsel q5 f5 reg6 d0 d1 ce ck s/r dsel q6 f6 reg7 d0 d1 ce ck s/r dsel q7 f7 reg4 d0 d1 ce ck s/r dsel q4 f4 a b c d f5mode45 k3_3 k2_0 k2_1 k2_2 k2_3 k1_0 k1_1 k1_2 f5b k3_0 k3_1 k3_2 k1_3 k0_0 k0_1 k0_2 k0_3 f5a a b c d a b c d a b c d k0 k1 k2 k3 din3 din2 din1 din0 reg1 d0 d1 ce ck s/r dsel q1 f1 reg2 d0 d1 ce ck s/r dsel q2 f2 reg3 d0 d1 ce ck s/r dsel q3 f3 reg0 d0 d1 ce ck s/r dsel q0 f0 a b c d f5mode01 f5mode67 f5mode23 0 0 0 0 0 0 0 0 0 0 0 0 ce 0 0 0 1 1 1 0 0 0 0 1 0 1 0 1 0 1 0
lucent technologies inc. 13 data sheet june 1999 orca series 3c and 3t fpgas programmable logic cells (continued) look-up table operating modes the operating mode affects the functionality of the pfu input and output ports and internal pfu routing. for exam- ple, in some operating modes, the din[7:0] inputs are direct data inputs to the pfu latches/ffs. in memory mode, the same din[7:0] inputs are used as a 4-bit write data input bus and a 4-bit write address input bus into lut memory. table 3 lists the basic operating modes of the lut. figure 4figure 10 show block diagrams of the lut operating modes. the accompanying descriptions demonstrate each modes use for generating logic. pfu control in p uts each pfu has five routable control inputs and an active-low, asynchronous global set/reset (gsrn) signal that affects all latches and ffs in the device. the five control inputs are clk, lsr, ce, aswe, and sel, and their functionality for each logic mode of the pfu (discussed subsequently) is shown in table 4. the clock signal to the pfu is clk, ce stands for clock enable, which is its primary function. lsr is the local set/reset signal that can be configured as synchronous or asynchronous. the selection of set or reset is made for each latch/ff and is not a function of the signal itself. aswe stands for add/subtract/write enable, which are its functions, along with being an optional clock enable, and sel is used to dynamically select between direct pfu input and lut output data as the input to the latches/ffs. all of the control signals can be disabled and/or inverted via the configuration logic. a disabled clock enable indi- cates that the clock is always enabled. a disabled lsr indicates that the latch/ff never sets/resets (except from gsrn). a disabled sel input indicates that din[7:0] pfu inputs are routed to the latches/ffs. for logic and ripple modes of the pfu, the lsr, ce, and aswe (as a clock enable) inputs can be disabled individually for each nibble (latch/ff[3:0], latch/ff[7:4]) and for the ninth ff. table 3. look-up table operating modes mode function logic 4- and 5-input luts; softwired luts; latches/ffs with direct input or lut input; cin as direct input to ninth ff or as pass through to cout. half logic/ half ripple upper four luts and latches/ffs in logic mode; lower four luts and latches/ffs in ripple mode; cin and ninth ff for logic or ripple functions. ripple all luts combined to perform ripple-through data functions. eight lut registers available for direct-in use or to register ripple output. ninth ff dedicated to ripple out, if used. the submodes of ripple mode are adder/subtractor, counter, multiplier, and comparator. memory all luts and latches/ffs used to create a 32 x 4 synchronous dual-port ram. can be used as single- port or as rom.
14 lucent technologies inc. data sheet june 1999 orca series 3c and 3t fpgas programmable logic cells (continued) table 4. control input functionality mode clk lsr ce aswe sel logic clk to all latches/ ffs lsr to all latches/ ffs, enabled per nib- ble and for ninth ff ce to all latches/ffs, selectable per nibble and for ninth ff ce to all latches/ffs, selectable per nibble and for ninth ff select between lut input and direct input for eight latches/ffs half logic/ half ripple clk to all latches/ ffs lsr to all latches/ff, enabled per nibble and for ninth ff ce to all latches/ffs, selectable per nibble and for ninth ff ripple logic control input select between lut input and direct input for eight latches/ffs ripple clk to all latches/ ffs lsr to all latches/ ffs, enabled per nib- ble and for ninth ff ce to all latches/ffs, selectable per nibble and for ninth ff ripple logic control input select between lut input and direct input for eight latches/ffs memory (ram) clk to ram port enable 2 port enable 1 write enable not used memory (rom) optional for sync. outputs not used not used not used not used lo g ic mode the pfu diagram of figure 3 represents the logic mode of operation. in logic mode, the eight luts are used individually or in flexible groups to implement user logic functions. the latches/ffs may be used in con- junction with the luts or separately with the direct pfu data inputs. there are three basic submodes of lut operation in pfu logic mode: f4 mode, f5 mode, and softwired lut (swl) mode. combinations of these submodes are possible in each pfu. f4 mode, shown simplified in figure 4, illustrates the uses of the basic 4-input luts in the pfu. the output of an f4 lut can be passed out of the pfu, captured at the luts associated latch/ff, or multiplexed with the adjacent f4 lut output using one of the f5[a:d] inputs to the pfu. only adjacent lut pairs (k 0 and k 1 , k 2 and k 3 , k 4 and k 5 , k 6 and k 7 ) can be multiplexed, and the output always goes to the even-numbered output of the pair. the f5 submode of the lut operation, shown simpli- fied in figure 4, indicates the use of 5-input luts to implement logic. 5-input luts are created from two 4-input luts and a multiplexer. the f5 lut is the same as the multiplexing of two f4 luts described previously with the constraint that the inputs to the f4 luts be the same. the f5[a:d] input is then used as the fifth lut input. the equations for the two f4 luts will differ by the assumed value for the f5[a:d] input, one f4 lut assuming that the f5[a:d] input is zero, and the other assuming it is a one. the selection of the appropriate f4 lut output in the f5 mux by the f5[a:d] signal creates a 5-input lut. any combination of f4 and f5 luts is allowed per pfu using the eight 16-bit luts. examples are eight f4 luts, four f5 luts, and a combination of four f4 plus two f5 luts. 5-5970(f) figure 4. simplified f4 and f5 logic modes k 7 f7 k 7 f6 k 6 f5d k 6 f6 k 5 f5 k 5 f4 k 4 f5c k 4 f4 k 3 f3 k 3 f2 k 2 f5b k 2 f2 k 1 f1 k 1 f0 k 0 f5a k 0 f0 k 7 /k 6 f6 k 5 /k 4 f4 k 3 /k 2 f2 k 1 /k 0 f0 f5 mode multiplexed f4 mode f4 mode
lucent technologies inc. 15 data sheet june 1999 orca series 3c and 3t fpgas programmable logic cells (continued) softwired lut submode uses f4 and f5 luts and internal pfu feedback routing to generate complex logic func- tions up to three lut-levels deep. figure 3 shows multiplexers between the k z [3:0] inputs to the pfu and the luts. these multiplexers can be independently configured to route certain lut outputs to the input of other luts. in this manner, very complex logic functions, some of up to 21 inputs, can be implemented in a single pfu at greatly enhanced speeds. figure 5 shows several softwired lut topologies. in this figure, each circle represents either an f4 or f5 lut. it is important to note that an lut output that is fed back for softwired use is still available to be registered or output from the pfu. this means, for instance, that a logic equation that is needed by itself and as a term in a larger equation need only be generated once and plc routing resources will not be required to use it in the larger equa- tion. figure 5. softwired lut topology examples 5-5753(f) f4 key: f5 4-input lut 5-input lut 5-5754(f) f4 f4 f4 f4 f4 f4 f4 f4 four 7-input functions in one pfu f5 f5 f5 f5 two 9-input functions in one pfu f5 f5 f5 f5 one 17-input function in one pfu f5 f5 f4 one 21-input function in one pfu f4 f4 f4 f4 f4 f4 f4 two of four 10-input functions in one pfu f4 f4 f4 f4 3 one of two 12-input functions in one pfu
16 16 lucent technologies inc. data sheet june 1999 orca series 3c and 3t fpgas programmable logic cells (continued) half-lo g ic mode series 3 fpgas are based upon a twin-quad architec- ture in the pfus. the byte-wide nature (eight luts, eight latches/ffs) may just as easily be viewed as two nibbles (two sets of four luts, four latches/ffs). the two nibbles of the pfu are organized so that any nib- ble-wide feature (excluding some softwired lut topolo- gies) can be swapped with any other nibble-wide feature in another pfu. this provides for very flexible use of logic and for extremely flexible routing. the half- logic mode of the pfu takes advantage of the twin- quad architecture and allows half of a pfu, k [7:4] and associated latches/ffs, to be used in logic mode while the other half of the pfu, k [3:0] and associated latches/ ffs, is used in ripple mode. in half-logic mode, the ninth ff may be used as a general-purpose ff or as a register in the ripple mode carry chain. ri pp le mode the pfu luts can be combined to do byte-wide ripple functions with high-speed carry logic. each lut has a dedicated carry-out net to route the carry to/from any adjacent lut. using the internal carry circuits, fast arithmetic, counter, and comparison functions can be implemented in one pfu. similarly, each pfu has carry-in (cin, fcin) and carry-out (cout, fcout) ports for fast-carry routing between adjacent pfus. the ripple mode is generally used in operations on two data buses. a single pfu can support an 8-bit ripple function. data buses of 4 bits and less can use the nibble-wide ripple chain that is available in half-logic mode. this nibble-wide ripple chain is also useful for longer ripple chains where the length modulo 8 is four or less. for example, a 12-bit adder (12 modulo 8 = 4) can be implemented in one pfu in ripple mode (8 bits) and one pfu in half-logic mode (4 bits), freeing half of a pfu for general logic mode functions. each lut has two operands and a ripple (generally carry) input, and provides a result and ripple (generally carry) output. a single bit is rippled from the previous lut and is used as input into the current lut. for lut k 0 , the ripple input is from the pfu cin or fcin port. the cin/fcin data can come from either the fast-carry routing (fcin) or the pfu input (cin), or it can be tied to logic 1 or logic 0. in the following discussions, the notations lut k 7 /k 3 and f[7:0]/f[3:0] are used to denote the lut that pro- vides the carry-out and the data outputs for full pfu ripple operation (k 7 , f[7:0]) and half-logic ripple operation (k 3 , f[3:0]), respectively. the ripple mode diagram in figure 6 shows full pfu ripple operation, with half-logic ripple connections shown as dashed lines. the result output and ripple output are calculated by using generate/propagate circuitry. in ripple mode, the two operands are input into k z [1] and k z [0] of each lut. the result bits, one per lut, are f[7:0]/f[3:0] (see figure 6). the ripple output from lut k 7 /k 3 can be routed on dedicated carry circuitry into any of four adja- cent plcs, and it can be placed on the pfu cout/ fcout outputs. this allows the plcs to be cascaded in the ripple mode so that nibble-wide ripple functions can be expanded easily to any length. result outputs and the carry-out may optionally be reg- istered within the pfu. the capability to register the ripple results, including the carry output, provides for improved counter performance and simplified pipelin- ing in arithmetic functions. figure 6. ripple mode 5-5755(f) f7 k 7 [1] k 7 [0] k 7 d q c c dq q7 regcout cout f6 k 6 [1] k 6 [0] k 6 d q q6 f4 k 4 [1] k 4 [0] k 4 d q q4 f3 k 3 [1] k 3 [0] k 3 d q q3 f2 k 2 [1] k 2 [0] k 2 d q q2 f1 k 1 [1] k 1 [0] k 1 d q q1 f5 k 5 [1] k 5 [0] k 5 d q q5 f0 k 0 [1] k 0 [0] k 0 d q q0 cin/fcin fcout
lucent technologies inc. 17 data sheet june 1999 orca series 3c and 3t fpgas programmable logic cells (continued) the ripple mode can be used in one of four submodes. the first of these is adder-subtractor submode . in this submode, each lut generates three separate out- puts. one of the three outputs selects whether the carry-in is to be propagated to the carry-out of the cur- rent lut or if the carry-out needs to be generated. if the carry-out needs to be generated, this is provided by the second lut output. the result of this selection is placed on the carry-out signal, which is connected to the next lut carry-in or the cout/fcout signal, if it is the last lut (k 7 /k 3 ). both of these outputs can be any equation created from k z [1] and k z [0], but in this case, they have been set to the propagate and gener- ate functions. the third lut output creates the result bit for each lut output connected to f[7:0]/f[3:0]. if an adder/subtrac- tor is needed, the control signal to select addition or subtraction is input on aswe, with a logic 0 indicating subtraction and a logic 1 indicating addition. the result bit is created in one-half of the lut from a single bit from each input bus k z [1:0], along with the ripple input bit. the second submode is the counter submode (see figure 7). the present count, which may be initialized via the pfu din inputs to the latches/ffs, is supplied to input k z [0], and then output f[7:0]/f[3:0] will either be incremented by one for an up counter or decre- mented by one for a down counter. if an up/down counter is needed, the control signal to select the direc- tion (up or down) is input on aswe with a logic 1 indi- cating an up counter and a logic 0 indicating a down counter. generally, the latches/ffs in the same pfu are used to hold the present count value. figure 7. counter submode 5-5756(f) f7 k 7 [0] k 7 d q c c dq q7 regcout cout f6 k 6 [0] k 6 d q q6 f4 k 4 [0] k 4 d q q4 f3 k 3 [0] k 3 d q q3 f2 k 2 [0] k 2 d q q2 f1 k 1 [0] k 1 d q q1 f5 k 5 [0] k 5 d q q5 f0 k 0 [0] k 0 d q q0 cin/fcin fcout
18 18 lucent technologies inc. data sheet june 1999 orca series 3c and 3t fpgas programmable logic cells (continued) in the third submode, multiplier submode , a single pfu can affect an 8 x 1 bit (4 x 1 for half-ripple mode) multiply and sum with a partial product (see figure 8). the multiplier bit is input at aswe, and the multiplicand bits are input at k z [1], where k 7 [1] is the most signifi- cant bit (msb). k z [0] contains the partial product (or other input to be summed) from a previous stage. if aswe is logical 1, the multiplicand is added to the par- tial product. if aswe is logical 0, 0 is added to the par- tial product, which is the same as passing the partial product. cin/fcin can bring the carry-in from the less significant pfus if the multiplicand is wider than 8 bits, and cout/fcout holds any carry-out from the multi- plication, which may then be used as part of the prod- uct or routed to another pfu in multiplier mode for multiplicand width expansion. ripple modes fourth submode features equality comparators. the functions that are explicitly available are a > b, a 1 b, and a < b, where the value for a is input on k z [0], and the value for b is input on k z [1]. a value of 1 on the carry-out signals valid argument. for example, a carry-out equal to 1 in ab submode indi- cates that the value on k z [0] is greater than or equal to the value on k z [1]. conversely, the functions a < b, a + b, and a > b are available using the same functions but with a 0 output expected. for example, a > b with a 0 output indicates a < b. table 5 shows each function and the output expected. if larger than 8 bits, the carry-out signal can be cas- caded using fast-carry logic to the carry-in of any adja- cent pfu. the use of this submode could be shown using figure 6, except that the cin/fcin input for the least significant pfu is controlled via configuration. key: c = configuration data. figure 8. multiplier submode table 5. ripple mode equality comparator functions and outputs equality function orca foundry submode true, if carry-out is: a > ba > b1 a < ba < b1 a 1 ba 1 b1 a < b a > b0 a > b a < b0 a = b a 1 b0 5-5757(f) k 7 [1] k 7 [0] + d q c c dq 1 0 0 k 7 aswe k 4 [1] k 4 [0] + d q 1 0 0 k 4 k 3 [1] k 3 [0] + d q 1 0 0 k 3 k 2 [1] k 2 [0] + d q 1 0 0 k 2 k 1 [1] k 1 [0] + d q 1 0 0 k 1 k 6 [1] k 6 [0] + d q 1 0 0 k 6 k 5 [1] k 5 [0] + d q 1 0 0 k 5 k 0 [1] k 0 [0] + d q 1 0 0 k 0 f7 q7 regcout cout f6 q6 f4 q4 f3 q3 f2 q2 f1 q1 f5 q5 f0 q0
lucent technologies inc. 19 data sheet june 1999 orca series 3c and 3t fpgas programmable logic cells (continued) memor y mode the series 3 pfu can be used to implement a 32 x 4 (128-bit) synchronous, dual-port random access memory (ram). a block diagram of a pfu in memory mode is shown in figure 9. this ram can also be configured to work as a single-port memory and because initial values can be loaded into the ram during configuration, it can also be used as a read-only memory (rom). figure 9. memory mode the pfu memory mode uses all luts and latches/ffs including the ninth ff in its implementation as shown in figure 9. the read address is input at the k z [3:0] and f5[a:d] inputs where k z [0] is the lsb and f5[a:d] is the msb, and the write address is input on cin (msb) and din[7, 5, 3, 1], with din[1] being the lsb. write data is input on din[6, 4, 2, 0], where din[6] is the msb, and read data is available combinatorially on f[6, 4, 2, 0] and registered on q[6, 4, 2, 0] with f[6] and q[6] being the msb. the write enable signal is input at aswe, and two write port enables are input on ce and lsr. the pfu clk signal is used to synchronously write the data. the polarities of the clock, write enable, and port enables are all programmable. write-port enables may be disabled if they are not to be used. 5-5969(f) q6 q4 q2 q0 d 5 q cin(wa4) k z [3:0] 4 f5[a:d] d q din7(wa3) d q din5(wa2) d q din3(wa1) d q din1(wa0) d q din6(wd3) d q din4(wd2) d q din2(wd1) d q din0(wd0) d q aswe(wren) en s/r ce(wpe1) lsr(wpe2) clk 4 write write read read 4 f6 f4 f2 f0 d q d q d q d q write ram clock address[4:0] address[4:0] data[3:0] data[3:0] enable
20 20 lucent technologies inc. data sheet june 1999 orca series 3c and 3t fpgas programmable logic cells (continued) data is written to the write data, write address, and write enable registers on the active edge of the clock, but data is not written into the ram until the next clock edge one-half cycle later. the read port is actually asynchronous, providing the user with read data very quickly after setting the read address, but timing is also provided so that the read port may be treated as fully synchronous for write then read applications. if the read and write address lines are tied together (main- taining msb to msb, etc.), then the dual-port ram operates as a synchronous single-port ram. if the write enable is disabled, and an initial memory contents is provided at configuration time, the memory acts as a rom (the write data and write address ports and write port enables are not used). wider memories can be created by operating two or more memory mode pfus in parallel, all with the same address and control signals, but each with a different nibble of data. to increase memory word depth above 32, two or more plcs can be used. figure 10 shows a 128 x 8 dual-port ram that is implemented in eight plcs. this figure demonstrates data path width expan- sion by placing two memories in parallel to achieve an 8-bit data path. depth expansion is applied to achieve 128 words deep using the 32-word deep pfu memo- ries. in addition to the pfu in each plc, the slic (described in the next section) in each plc is used for read address decodes and 3-state drivers. the 128 x 8 ram shown could be made to operate as a single-port ram by tying (bit-for-bit) the read and write addresses. to achieve depth expansion, one or two of the write address bits (generally the msbs) are routed to the write port enables as in figure 10. for 2 bits, the bits select which 32-word bank of ram of the four available from a decode of two wpe inputs is to be written. simi- larly, 2 bits of the read address are decoded in the slic and are used to control the 3-state buffers through which the read data passes. the write data bus is common, with separate nibbles for width expan- sion, across all plcs, and the read data bus is com- mon (again, with separate nibbles) to all plcs at the output of the 3-state buffers. figure 10 also shows a new optional capability to pro- vide a read enable for rams/roms in series 3 using the slic cell. the read enable will 3-state the read data bus when inactive, allowing the write data and read data buses to be tied together if desired. figure 10. memory mode expansion example128 x 8 ram 5-5749(f) rd[7:0] we wa[6:0] ra[6:0] clk wa ra wpe0 wpe1 we wd[7:4] 5 5 4 plc 8 wd[7:0] 8 7 7 wa ra wpe0 wpe1 we rd[3:0] wd[3:0] 5 5 4 plc rd[7:4] wa ra wpe0 wpe1 we wd[7:4] 5 5 4 plc wa ra wpe0 wpe1 we rd[3:0] wd[3:0] 5 5 4 plc rd[7:4] re 4 4 4 4 pfu pfu pfu pfu slic slic slic slic
lucent technologies inc. 21 data sheet june 1999 orca series 3c and 3t fpgas programmable logic cells (continued) supplemental logic and interconnect cell (slic) each plc contains a supplemental logic and intercon- nect cell (slic) embedded within the plc routing, out- side of the pfu. as its name indicates, the slic performs both logic and interconnect (routing) func- tions. its main features are 3-statable, bidirectional buff- ers, and a pa l -like decoder capability. figure 11 shows a diagram of a slic with all of its features shown. all modes of the slic are not available at one time. each slic contains ten bidirectional (bidi) buffers, each buffer capable of driving left and/or right out of the slic. these bidi buffers are twin-quad in nature and are segregated into two groups of four (nibbles) and a third group of two for control. each of these groups of bidis can drive from the left (bli[9:0]) to the right (bro[9:0]), the right (bri[9:0]) to the left (blo[9:0]), or from the central input (i[9:0]) to the left and/or right. this central input comes directly from the pfu outputs (o[9:0]). each of the bidis in the nibble-wide groups also has a 3-state buffer capability, but not the third group. there is one 3-state control (tri) for each slic, with the capability to invert or disable the 3-state control for each group of four bidis. separate 3-state control for each nibble-wide group is achievable by using the slics decoder (dec) output, driven by the group of two bidis, to control the 3-state of one bidi nibble while using the tri signal to control the 3-state of the other bidi nibble. figure 12 and figure 13 show the slic in buffer mode with available 3-state control from the tri and dec signals. if the entire slic is acting in a buffer capacity, the dec output may be used to gen- erate a constant logic 1 (vhi) or logic 0 (vlo) signal for general use. the slic may also be used to generate pa l -like and- or with optional invert (aoi) functions or a decoder of up to 10 bits. each group of buffers can feed into an and gate (4-input and for the nibble groups and 2- input and for the other two buffers). these and gates then feed into a 3-input gate that can be configured as either an and gate or an or gate. the output of the 3- input gate is invertible and is output at the dec output of the slic. figure 16 shows the slic in full decoder mode. the functionality of the slic is parsed by the two nibble-wide groups and the 2-bit buffer group. each of these groups may operate independently as bidi buff- ers (with or without 3-state capability for the nibble- wide groups) or as a pa l /decoder. as discussed in the memory mode section, if the slic is placed into one of the modes where it contains both buffers and a decode or aoi function (e.g., buf_buf_dec mode), the dec output can be gated with the 3-state input signal. this allows up to a 6-input decode (e.g., buf_dec_dec mode) plus the 3-state input to control the enable/disable of up to four buffers per slic. figure 12figure 16 show several configu- rations of the slic, while table 6 shows all of the possi- ble modes. table 6. slic modes mode # mode buf [3:0] buf [7:4] buf [9:8] 1 buffer buffer buffer buffer 2 buf_buf_dec buffer buffer decoder 3 buf_dec_buf buffer decoder buffer 4 buf_dec_dec buffer decoder decoder 5 dec_buf_buf decoder buffer buffer 6 dec_buf_dec decoder buffer decoder 7 dec_dec_buf decoder decoder buffer 8 decoder decoder decoder decoder
22 22 lucent technologies inc. data sheet june 1999 orca series 3c and 3t fpgas programmable logic cells (continued) figure 11. slic all modes diagram figure 12. buffer mode 5-5744(f) bri9 i9 bli9 bri8 i8 bli8 bri7 i7 bli7 bri6 i6 bli6 bri5 i5 bli5 bri4 i4 bli4 bri3 i3 bli3 bri2 i2 bli2 bri1 i1 bli1 bri0 i0 bli0 bl09 br09 bl08 br08 bl07 br07 bl06 br06 bl05 br05 bl04 br04 bl03 br03 bl02 br02 bl01 br01 bl00 br00 dec dec 0/1 0/1 tri 0/1 0/1 high z when low 5-5745(f) bri9 i9 bli9 bri8 i8 bli8 bri7 i7 bli7 bri6 i6 bli6 bri5 i5 bli5 bri4 i4 bli4 bri3 i3 bli3 bri2 i2 bli2 bri1 i1 bli1 bri0 i0 bli0 bl09 br09 bl08 br08 bl07 br07 bl06 br06 bl05 br05 bl04 br04 bl03 br03 bl02 br02 bl01 br01 bl00 br00 tri 0/1 0/1 1 0 dec this can be used a vhi or vlo high z when low to generate
lucent technologies inc. 23 data sheet june 1999 orca series 3c and 3t fpgas programmable logic cells (continued) figure 13. buffer-buffer-decoder mode figure 14. buffer-decoder-buffer mode 5-5746(f) bri9 bli9 bri8 bli8 bri7 i7 bli7 bri6 i6 bli6 bri5 i5 bli5 bri4 i4 bli4 bri3 i3 bli3 bri2 i2 bli2 bri1 i1 bli1 bri0 i0 bli0 bl07 br07 bl06 br06 bl05 br05 bl04 br04 bl03 br03 bl02 br02 bl01 br01 bl00 br00 tri dec 1 1 1 1 high z when low high z when low 5-5747(f) bri7 bli7 bri6 bli6 bri5 bli5 bri4 bli4 bri3 i3 bli3 bri2 i2 bli2 bri1 i1 bli1 bri0 i0 bli0 bl03 br03 bl02 br02 bl01 br01 bl00 br00 tri dec bri9 i9 bli9 bri8 i8 bli8 bl09 br09 bl08 br08 1 1 high z when low
24 24 lucent technologies inc. data sheet june 1999 orca series 3c and 3t fpgas programmable logic cells (continued) figure 15. buffer-decoder-decoder mode figure 16. decoder mode 5-5750(f) bri7 bli7 bri6 bli6 bri5 bli5 bri4 bli4 bri3 i3 bli3 bri2 i2 bli2 bri1 i1 bli1 bri0 i0 bli0 bl03 br03 bl02 br02 bl01 br01 bl00 br00 tri dec bri9 bli9 bri8 bli8 1 1 high z when low 5-5748(f) bri7 bli7 bri6 bli6 bri5 bli5 bri4 bli4 bri3 bli3 bri2 bli2 bri1 bli1 bri0 bli0 dec bri9 bli9 bri8 bli8
lucent technologies inc. 25 data sheet june 1999 orca series 3c and 3t fpgas programmable logic cells (continued) plc latches/flip-flops the eight general-purpose latches/ffs in the pfu can be used in a variety of configurations. in some cases, the configuration options apply to all eight latches/ffs in the pfu and some apply to the latches/ffs on a nibble- wide basis where the ninth ff is considered indepen- dently. for other options, each latch/ff is independently programmable. in addition, the ninth ff can be used for a variety of functions. table 7 summarizes these latch/ff options. the latches/ffs can be configured as either positive- or negative-level sensitive latches, or positive or negative edge-triggered flip-flops (the ninth register can only be ff). all latches/ffs in a given pfu share the same clock, and the clock to these latches/ffs can be inverted. the input into each latch/ff is from either the corresponding lut output (f[7:0]) or the direct data input (din[7:0]). the latch/ff input can also be tied to logic 1 or to logic 0, which is the default. * not available for ff[8]. the eight latches/ffs in a pfu share the clock (clk) and options for clock enable (ce), local set/reset (lsr), and front-end data select (sel) inputs. when ce is dis- abled, each latch/ff retains its previous value when clocked. the clock enable, lsr, and sel inputs can be inverted to be active-low. the set/reset operation of the latch/ff is controlled by two parameters: reset mode and set/reset value. when the global set/reset ( gsrn ) and local set/reset (lsr) signals are not asserted, the latch/ff operates normally. the reset mode is used to select a synchronous or asynchronous lsr operation. if synchronous, lsr has the option to be enabled only if clock enable (ce or aswe) is active or for lsr to have priority over the clock enable input, thereby setting/resetting the ff inde- pendent of the state of the clock enable. the clock enable is supported on ffs, not latches. it is imple- mented by using a 2-input multiplexer on the ff input, with one input being the previous state of the ff and the other input being the new data applied to the ff. the select of this 2-input multiplexer is clock enable (ce or aswe), which selects either the new data or the previ- ous state. when the clock enable is inactive, the ff out- put does not change when the clock edge arrives. table 7. configuration ram controlled latch/ flip-flop operation function options common to all latches/ffs in pfu lsr operation asynchronous or synchronous clock polarity noninverted or inverted front-end select* direct (din[7:0]) or from lut (f[7:0]) lsr priority either lsr or ce has priority latch/ff mode latch or flip-flop enable gsrn gsrn enabled or has no effect on pfu latches/ffs set individually in each latch/ff in pfu set/reset mode set or reset by group (latch/ff[3:0], latch/ff[7:4], and ff[8]) clock enable ce or aswe or none lsr control lsr or none
26 26 lucent technologies inc. data sheet june 1999 orca series 3c and 3t fpgas programmable logic cells (continued) the gsrn signal is only asynchronous, and it sets/ resets all latches/ffs in the fpga based upon the set/ reset configuration bit for each latch/ff. the set/reset value determines whether gsrn and lsr are set or reset inputs. the set/reset value is independent for each latch/ff. a new option is available to disable the gsrn function per pfu after initial device configura- tion. the latch/ff can be configured to have a data front- end select. two data inputs are possible in the front- end select mode, with the sel signal used to select which data input is used. the data input into each latch/ff is from the output of its associated lut, f[7:0], or direct from din[7:0], bypassing the lut. in the front- end data select mode, both signals are available to the latches/ffs. if either or both of these inputs is unused or is unavail- able, the latch/ff data input can be tied to a logic 0 or logic 1 instead (the default is logic 0). the latches/ffs can be configured in three basic modes: 1. local synchronous set/reset: the input into the pfus lsr port is used to synchronously set or reset each latch/ff. 2. local asynchronous set/reset: the input into lsr asynchronously sets or resets each latch/ff. 3. latch/ff with front-end select, lsr either synchro- nous or asynchronous: the data select signal selects the input into the latches/ffs between the lut output and direct data in. for all three modes, each latch/ff can be indepen- dently programmed as either set or reset. figure 17 provides the logic functionality of the front-end select, global set/reset, and local set/reset operations. the ninth pfu ff, which is generally associated with registering the carry-out signal in ripple mode func- tions, can be used as a general-purpose ff. it is only an ff and is not capable of being configured as a latch. because the ninth ff is not associated with an lut, there is no front-end data select. the data input to the ninth ff is limited to the cin input, logic 1, logic 0, or the carry-out in ripple and half-logic modes. ke y : c = confi g uration data. fi g ure 17. latch/ff set/reset confi g urations din logic 0 logic 1 f ce d s_set s_reset clk set reset q lsr gsrn cd ce/aswe d clk set reset lsr cd ce ce/aswe d clk set reset cd ce ce/aswe din sel gsrn din logic 0 logic 1 f din logic 0 logic 1 f lsr gsrn q q
lucent technologies inc. 27 data sheet june 1999 orca series 3c and 3t fpgas programmable logic cells (continued) plc routing resources generally, the orca foundry development system is used to automatically route interconnections. interac- tive routing with the orca foundry design editor (epic) is also available for design optimization. to use epic for interactive layout, an understanding of the routing resources is needed and is provided in this sec- tion. the routing resources consist of switching circuitry and metal interconnect segments. generally, the metal lines which carry the signals are designated as routing seg- ments. the switching circuitry connects the routing segments, providing one or more of three basic func- tions: signal switching, amplification, and isolation. a net running from a pfu or pic output (source) to a plc or pic input (destination) consists of one or more routing segments, connected by switching circuitry called configurable interconnect points (cips). the following sections discuss plc, pic, and interquad routing resources. this section discusses the plc switching circuitry, intra-plc routing, inter-plc routing, and clock distribution. confi g urable interconnect points the process of connecting routing segments uses three basic types of switching circuits: two types of con- figurable interconnect points (cips) and bidirectional buffers (bidis). the basic element in cips is one or more pass transistors, each controlled by a configura- tion ram bit. the two types of cips are the mutually exclusive (or multiplexed) cip and the independent cip. a mutually exclusive set of cips contains two or more cips, only one of which can be on at a time. an inde- pendent cip has no such restrictions and can be on independent of the state of other cips. figure 18 shows an example of both types of cips. ke y : c = confi g uration data. 5-5973(c) fi g ure 18. confi g urable interconnect point 3-statable bidirectional buffers bidirectional buffers, previously described in the slic section of the programmable logic cell discussion, pro- vide isolation as well as amplification for signals routed a long distance. bidirectional buffers are also used to route signals diagonally in the plc (described later in the subsection entitled intra-plc routing), and bidis can be used to indirectly route signals through the switching routing (xsw) segments. any number from zero to ten bidis can be used in a given plc. multiplexed cip a b c o a b c o cd independent cip a b cd b a = 2
28 lucent technologies inc. data sheet june 1999 orca series 3c and 3t fpgas programmable logic cells (continued) general routing structure routing resources in series 3 fpgas generally consist of routing segments in groups of ten, with varying lengths and connectivity to logic and other routing resources. the varying lengths of routing segments provides a hierarchy of routing capability from chip-length routes to routes within a plc. the hierarchical nature of the routing provides the orca foundry development tools with the necessary resources to route a design completely and to optimize the routing for system speed while reducing the overall power required by the device. within each group of ten routing segments there is an equivalency of connectivity between pairs of segments. these pairs are segments: [0, 4] and [1, 5] and [2, 6] and [3, 7] and [8, 9]. the equivalency in connectivity ensures that signals on either segment in a pair have the same capability to get to a given destination. this, in turn, allows for signal distribution from a source to varying destinations without using special routing. it also provides for routing flexibility by ensuring that one segment position will not become so congested as to preclude routing a bus or group of signals and allows easy connectivity from either of the twin quads in a source pfu to either of the twin quads in any destination pfu. having ten segments in a group is significant in that it provides for routing a byte of data and two control signals or parity. due to the equivalent pairs of segments, this can also be viewed as routing two nibbles each with a control signal. figure 19 is an overview of the routing for a single plc. 5-5766(f) fi g ure 19. sin g le plc view of inter-plc route se g ments 2 of 5 line-by-line fins pfu output slic switching sur[9:0] bl[9:0] vxl[9:0] vx5[9:0] vx1l[9:0] sul[9:0] vx1r[9:0] fc lck vck vxh[9:0] bl[9:0] hxh[9:0] hx1u[9:0] hck fc sll[9:0] hx1b[9:0] hx5[9:0] hxl[9:0] br[9:0] sul[9:0] bl[9:0] fc sul[9:0] br[9:0] lck sll[9:0] fc slr[9:0] 5 2 5 2 5 2 key: configurable signal line breaks
lucent technologies inc. 29 data sheet june 1999 orca series 3c and 3t fpgas programmable logic cells (continued) intra-plc routin g the function of the intra-plc routing resources is to connect the pfus input and output ports to the routing resources used for entry to and exit from the plc. this routing provides pfu feedback, corner turning, or switching from one type of routing resource to another. flexible in p ut structure ( fins ) the flexible input switching structure ( fins ) in each plc of the orca series 3 provides for the flexibility of a crossbar switch from the routing resources to the pfu inputs while taking advantage of the routability of shared inputs. connectivity between the plc routing resources and the pfu inputs is provided in two stages. the primary fins switch has 50 inputs that connect the plc routing to the 35 inputs on the sec- ondary switch. the outputs of the second switch con- nect to the 50 pfu inputs. the switches are implemented to provide connectivity for bused signals and individual connections. pfu out p ut switchin g the pfu outputs are switched onto plc routing resources via the pfu output multiplexer (omux). the pfu output switching segments from the output multi- plexer provide ten connections to the plc routing out of 18 possible pfu outputs (f[7:0], q[7:0], dout, regcout). these output switching segments con- nect segment for segment to the sur, sul, slr, and sll switching segments described below (e.g., o4 connects only to sur4, not sur5). the output switch- ing segments also feed directly into the slic on a seg- ment-by-segment basis. this connectivity is also described below. switching routing segments (xsw) there are four sets of switching routing segments in each plc. each set consists of ten switching elements: sul[9:0], sur[9:0], sll[9:0], and slr[9:0], tradition- ally labeled for the upper-left, upper-right, lower-left, and lower-right sections of the pfus, respectively. the xsw routing segments connect to the pfu inputs and outputs as well as the bidi routing segments, to be described later. they also connect to both the horizon- tal and vertical x1 and x5 routing segments (inter-plc routing resources, described later) in their specific cor- ner. xsw segments can be used for fast connections between adjacent plcs or pics without requiring the use of inter-plc routing resources. this capability not only increases signal speed on adjacent plc routing, but also reduces routing congestion on the principal inter-plc routing resources. the sll and sur seg- ments combine to provide connectivity to the plcs to the left and right of the current plc; the slr and sul segments combine to provide connectivity to the plcs above and below the current plc. fast routes on switching segments to diagonally adja- cent plcs/pics are possible using the bidi routing segments (discussed below) and the sll and slr switching segments. the br bidi routing segments combine with the sul switching segments of the plc below and to the right of the current plc to connect to that plc. the bl bidi routing segments combine with the sll switching segments of the plc above and to the right of the current plc to connect to that plc. these fast diagonal connections provide a great amount of flexibility in routing congested areas of logic and in shifting data on a per-plc basis such as per- forming implicit multiplications/divisions in routing between functional logic elements. switching routing segments are also the chief means by which signals are transferred between the inter-plc routing resources and the pfu. each set of switching segments has connectivity to the x1 routing segments, and there is varying connectivity to the x5, xh, and xl inter-plc routing segments. detailed information on switching segment/inter-plc routing connectivity is provided later in this section in the inter-plc routing resources subsection.
30 30 lucent technologies inc. data sheet june 1999 orca series 3c and 3t fpgas programmable logic cells (continued) bidi routin g and slic connectivit y the slic is connected to the rest of the plc by the bidirectional (bidi) routing segments and the pfu out- put switching segments coming from the pfu output multiplexer. the bidi routing segments (xbid) are labeled as bl for bidi-left and br for bidi-right. each set of br and bl xbid segments is composed of ten bidirectional lines (note that these lines are diagramed as ten input lines to the slic and ten output lines from the slic that can be used in a mutually exclusive fash- ion). because the slic is connected directly to the out- puts of the pfu, it provides great flexibility in routing via the xbid segments. the pfu routing segments, o[9:0], only connect to their respective line in the sll, sul, sur, and slr switching segment groups. that is, o9 only connects to sll9, sul9, sur9, and slr9. the bidi lines provide the capability to connect to the other member of the routing set. that means, for example, that o9 can be routed to br8 or bl8. this connectivity can be used as a means to distribute or gather signals on intra-plc routing without disturbing inter-plc resources. as described in the switching routing seg- ments subsection, the bidi routing segments are also used for routes to a diagonally adjacent pfu. in addition to the intra-plc connections, the xbid and output switching segments also have connectivity to the x1, x5, and xl inter-plc routing resources, provid- ing an alternate routing path rather than using plc xsw segments. these connections also provide a path to the 3-state buffers in the slic without encumbering the xsw segments. in this manner, buffering or 3-state control can be added to inter-plc routing without dis- turbing local functionality within a pfu. control signal and fast-carry routing pfu control signal and the fast-carry routing are per- formed using the fins structure and several dedicated routing paths. the fast-carry (fc) routing resources consist of a dedicated bidirectional segment between each orthogonal pair of plcs. this means that a fast- carry can go to or come from each plc to the right or left, above or below the subject plc. the fins struc- ture is used to control the switching of these fast-carry paths between the fast-carry input (fcin) and fast- carry output (fcout) ports of the pfu. the pfu control inputs (ce, sel, lsr, aswe) and cin can be reached via the fins by two special routing segments, e1 and e2. the e1 routing segment pro- vides connectivity between all of the xbid routing seg- ments and the fins . it is unidirectional from the bidi routing to the fins . e1 also provides connectivity to the pfu clock input via fins for a local clock signal. the e2 segment connects the slic dec output to the fins and to a group of cips that provide bidirectional con- nectivity with all of the bidi routing segments. this allows the dec signal to be used in the pfu and/or routed on the bidi segments. it also allows signals to be routed to the pfu on the xbid segments if the slic dec output is not used. there is also a dedicated routing segment from the fins to the slic tri input used for bidi buffer 3-state control.
lucent technologies inc. 31 data sheet june 1999 orca series 3c and 3t fpgas programmable logic cells (continued) inter-plc routin g resources the inter-plc routing is used to route signals between plcs. the routing segments occur in groups of ten, and differ in the numbers of plcs spanned. the x1 routing segments span one plc, the x5 routing seg- ments span five plcs, the xh routing segments span one-half the width (height) of the plc array, and the xl routing segments span the width (height) of the plc array. all types of routing segments run in both horizon- tal and vertical directions. table 8 shows the groups of inter-plc routing seg- ments in each plc. in the table, there are two rows/col- umns for x1 lines. they are differentiated by a t for top, b for bottom, l for left, and r for right. in the orca foundry design editor representation, the horizontal x1 routing segments are located above and below the pfu. the two groups of vertical segments are located on the left side of the pfu. the xl and x5 routing seg- ments only run below and to the left of the pfu, while the xh segments only run above and to the right of the pfu. the indexes specify individual routing segments within a group. for example, the vx5[2] segment runs vertically to the left of the pfu, spans five plcs, and is the third line in the 10-bit wide group. plcs are arranged like tiles on the orca device. breaks in routing occur at the middle of the tile (e.g., x1 lines break in the middle of each plc) and run across tiles until the next break. figure 20 provides a global view of inter-plc routing resources across multiple plcs. x1 routing segments. there are a total of 40 x1 rout- ing segments per plc: 20 vertical and 20 horizontal. each of these are subdivided into two, 10-bit wide buses: hx1t[9:0], hx1b[9:0], vx1l[9:0], and vx1r[9:0]. an x1 segment is one plc long. if a signal net is longer than one plc, an x1 segment can be lengthened to n times its length by turning on n C 1 cips. a signal is routed onto an x1 route segment via the switching rout- ing segments or bidi routing segments which also allows the x1 route segment to be connected to other inter-plc segments of different lengths. corner turning between x1 segments is provided through direct con- nections, xsw segments, and xbid segments. x5 routing segments. there are two sets of ten x5 routing segments per plc. one set (vx5[9:0]) runs ver- tically, and the other (hx5[9:0]) runs horizontally. each x5 segment traverses five plcs before it is broken by a cip. two x5 segments in each group break in each plc. the two that break are in an equivalent pair; for example, x5[0] and x5[4]. the x5 segments that break shift by one at the next plc. for example, if hx5[0] and hx5[4] are broken at the current plc, hx5[1] and hx5[5] will be broken at the plc to the right of the current plc. there are direct connections to the bidi routing segments in the plc at which the x5 segments break, on both sides of the break. signal corner turning is enabled by cips in each plc that allow the broken x5 segments to directly connect to the broken x5 seg- ments that run in the orthogonal direction. x5 corner turning can also be accomplished via the xsw and xbid segments in a plc. in addition, the x5 segments are connected to the fins and pfu outputs on a bit- by-bit basis by the xsw segments. x5 segments can be connected for signal runs in multiples of five plcs, or they can be combined with x1 and xh routing segments for runs of varying distances. table 8. inter-plc routing resources horizontal routin g se g ments vertical routin g se g ments distance s p anned hx1u [ 9:0 ] vx1r [ 9:0 ] one plc hx1b [ 9:0 ] vx1l [ 9:0 ] one plc hx5 [ 9:0 ] vx5 [ 9:0 ] five plcs hx5 [ 9:0 ] vx5 [ 9:0 ] five plcs hxl [ 9:0 ] vxl [ 9:0 ] plc arra y hxh [ 9:0 ] vxh [ 9:0 ] 1/2 plc arra y hclk vclk plc arra y
32 lucent technologies inc. data sheet june 1999 orca series 3c and 3t fpgas programmable logic cells (continued) 5-5767(f) fi g ure 20. multi p le plc view of inter-plc routin g pfu pfu pfu pfu pfu pfu pfu pfu pfu hxh[9:0] hx1[9:0] hclk hx1[9:0] hx5[9:0] hxl[9:0] hxh[9:0] hx1[9:0] hclk hx1[9:0] hx5[9:0] hxl[9:0] hx1[9:0] hx5[9:0] hxl[9:0] hxh[9:0] hx1[9:0] hclk vx1l[9:0] vx5[9:0] vclk vxh[9:0] vx1[9:0] vxl[9:0] vx5[9:0] vclk vxh[9:0] vxl[9:0] vx5[9:0] vx1[9:0] vclk vxh[9:0] vx1[9:0] vx1[9:0] vx1[9:0] vx1[9:0] 10 2 2 10 2 10 2 10 2 10 2 10 2 10 2 10 2 10 2 10 10 2 10 2 10 2 10 2 10 2 10 2 10 2 10 2 slic slic slic slic slic slic slic slic slic plc boundary 2 of 10 line-by-line 10 2 key: configurable signal-line breaks:
lucent technologies inc. 33 data sheet june 1999 orca series 3c and 3t fpgas programmable logic cells (continued) xl routing lines. the xl routing lines run vertically and horizontally the height and width of the array, respectively. there are a total of 20 xl routing lines per plc: ten horizontal (hxl[9:0]) and ten vertical (vxl[9:0]). each of the xl lines connects to the pic routing at either end. the xl lines are intended prima- rily for global signals that must travel long distances and require minimum delay and/or skew, such as clocks or 3-state buses. each xl line (also called a long line) drives a buffer in each plc that can drive onto the horizontal and verti- cal local clock routing segments (lclk) in the plc. also, two out of each group of ten xl segments in each plc can be driven by a buffer attached to a clock spine (described later) allowing local distribution of global clock signals. more general-purpose connections to the long lines can be made through the xbid segments in a plc. each long line is connected to an xbid segment on a bit-by-bit basis. these bidi connections allow cor- ner turning from horizontal to vertical long lines, and connection between long lines and x1 or x5 segments. xh routing segments . ten by-half (xh) routing seg- ments run horizontally (hxh[9:0]) and ten xh routing segments run vertically (vxh[9:0]) in each row and col- umn in the array. these routing segments travel a dis- tance of one-half the plc array before being broken in the middle of the array in the interquad area (discussed later). they also connect at the periphery of the fpga to the pics, like the xl lines. xh routing segments con- nect to the plcs only by switching segments. they are intended for fast signal interconnect. clock (and global ce and lsr) routing segments. for a very fast and low-skew clock (or other global sig- nal tree), clock routing segments run the entire height and width of the plc array. there are two clock routing segments per plc: one horizontal (hclk) and one ver- tical (vclk). the source for these clock routing seg- ments can be any of the i/o buffers in the pic, the series 3 expressclk inputs, user logic, or the pro- grammable clock manager ( pcm ). the horizontal clock routing segments (hclk) are alternately driven by the left and right pics. the vertical clock routing segments (vclk) are alternately driven by the top and bottom pics. the clock routing segments are designed to be a clock spine. in each plc, there is a fast connection available from the clock segment to a long-line driver (described earlier). with this connection, one of the clock routing segments in each plc can be used to drive one of the ten xl routing segments perpendicular to it, which, in turn, creates a clock spine tree. this feature is dis- cussed in detail in the clock distribution network sec- tion. special connectivity is provided in each plc to connect the clock enable signals (ce and aswe) and the lsr signal to the clock network for fast global control signal distribution. ce and aswe have a special connection to the horizontal clock spine, and lsr has a special connection to the vertical clock spine. this allows both signals to be routed globally within the same plc, if desired; however, this will consume some of the resources available for clock signal routing. if using these spines, the clock enable signal must come from the right or left edge of the device, and the lsr signal must come from the top or bottom of the device due to their horizontal and vertical connectivity, respectively, to the clock network. minimizin g routin g dela y the cip is an active element used to connect two rout- ing segments. as an active element, it adds signifi- cantly to the resistance and capacitance of a routing network (net), thus increasing the nets delay. the advantage of the x1 segment over an x5 segment is routing flexibility. a net from one plc to the next is eas- ily routed by using x1 routing segments. as more cips are added to a net, the delay increases. to increase speed, routes that are greater than two plcs away are routed on the x5 routing segments because a cip is located only in every fifth plc. a net that spans eight plcs requires seven x1 routing segments and six cips. using x5 routing segments, the same net uses two routing segments and one cip.
34 34 lucent technologies inc. data sheet june 1999 orca series 3c and 3t fpgas programmable logic cells (continued) plc architectural description figure 21 is an architectural drawing of the plc (as seen in orca foundry) that reflects the pfu, the rout- ing segments, and the cips. a discussion of each of the letters in the drawing follows. a . these are switchin g routin g se g ments ( xsw ) that g ive the router flexibilit y . in g eneral switchin g theor y , the more levels of indirection there are in the routin g , the more routable the network is. the xsw se g - ments can also connect to the xsw lines in ad j acent plcs. b . these cips connect the x1 routin g . these are located in the middle of the plc to allow the block to connect to either the left end of the horizontal x1 se g ment from the ri g ht or the ri g ht end of the hori- zontal x1 se g ment from the left, or both. b y s y mme- tr y , the same principle is used in the vertical direction. c . this set of cips is used to connect the x1 and x5 nets to the xsw se g ments or to other x1 and x5 nets. the cips on the ma j or dia g onal allow data to be transmitted on a bit-b y -bit basis from x1 nets to the xsw se g ments and between the x1 and x5 nets. d . this structure is the supplemental lo g ic and inter- connect cell, or slic. it contains 3-statable bidirec- tional buffers and lo g ic for buildin g decoders and and-or-invert t y pe structures. e . these are the primar y and secondar y elements of the flexible input structure or fins . fins is a switch matrix that provides hi g h connectivit y while retainin g routin g capabilit y . fins also includes feedback paths for softwired lut implementation. f . this is the pfu output switch matrix. it is a complex switch network which, like the fins at the input, pro- vides hi g h connectivit y and maintains routabilit y . g . this set of cips allows an xbid se g ment to transfer a si g nal to/from xsw se g ments on each side. the bidis can access the pfu throu g h the xsw se g - ments. these cips allow data to be routed throu g h the bidis for amplification or 3-state control and continue to another plc. the y also provide an alter- native routin g resource to improve routabilit y . h . these cips are used to transfer data from/to the xbid se g ments to/from the x1 and xl routin g se g - ments. these cips have been optimized to allow the bidi buffers to drive the loads usuall y seen when usin g each t y pe of routin g se g ment. i. clock input to pfu. j . these are the ten switched output routin g se g ments from the pfu. the y connect to the plc switchin g se g ments and are input to the slic. k . these lines deliver the auxiliar y si g nals clock enable ( ce ) , local set/reset ( lsr ) , front-end select ( sel ) , add/subtract/write enable ( aswe ) , as well as the carr y si g nals ( cin and fcin ) to the latches/ffs. l . this is the local clock buffer. an y of the horizontal and vertical xl lines can drive the clock input of the plc latches/ffs. the clock routin g se g ments ( vclk and hclk ) and multiplexers/drivers are used to connect to the xl routin g se g ments for low-skew, low-dela y g lobal si g nals. m . these routin g se g ments are used to route the fast- carr y si g nal to/from the nei g hborin g four plcs. the carr y -out ( cout ) and re g istered carr y -out ( reg- cout ) can also be routed out of the pfu. n . this is the e2 control routin g se g ment. it runs from the slic dec output to the fins and also provides connectivit y to all xbid se g ments. o . the xh routin g se g ments run one-half the len g th ( width ) of the arra y before bein g broken b y a cip. p . these cips connect the xh se g ments to the xsw se g ments. q .the xbid se g ments are used to connect the slic to the xsw se g ments, x1 se g ments, x5 se g ments, and xl lines, as well as providin g for dia g onal plc to plc connections. r . these cips provide connections from the xbid se g - ments to the e1/e2 routin g se g ments that feed pfu control inputs ce, lsr, cin, aswe, sel, and the clock input. alternativel y , these cips connect the bidi lines to the decoder ( dec ) output of the slic, for routin g the dec si g nal. s . these are clock spines ( vclk and hclk ) with the multiplexers and drivers to connect to the xl routin g se g ments. t . these cips connect xbid se g ments to switchin g se g ments in dia g onall y and ortho g onall y ad j acent pfus. u . these cips connect xsw se g ments to the pfu out- put se g ments. v . these cips connect xsw se g ments in ortho g onall y ad j acent pfus. w .this is the slic 3-state control routin g se g ment from the fins to the slic 3-state control. x. this is the e1 control routin g se g ment. it provides a pfu input path from all xbid se g ments. y. these cips are used to select which xbid se g ments are connected to the e1/e2 si g nal as described in ( r ) .
lucent technologies inc. 35 data sheet june 1999 orca series 3c and 3t fpgas pro g rammable lo g ic cells ( continued ) 5-5758(f) figure 21. plc architecture h s m g r l h h d r slic output switching pfu primary fins secondary fins b w y a b p m o q m o f pv k j u u u x a b h b g c h q q t m s q q l h t e e n q c c c a c c c a a a a c a a c c c c a
36 36 lucent technologies inc. data sheet june 1999 orca series 3c and 3t fpgas programmable input/output cells the programmable input/output cells (pics) are located along the perimeter of the device. the pics name is represented by a two-letter designation to indi- cate on which side of the device it is located followed by a number to indicate in which row or column it is located. the first letter, p, designates that the cell is a pic and not a plc. the second letter indicates the side of the array where the pic is located. the four sides are left (l), right (r), top (t), and bottom (b). the indi- vidual i/o pad is indicated by a single letter (either a, b, c, or d) placed at the end of the pic name. as an example, pl10a indicates a pad located on the left side of the array in the tenth row. each pic interfaces to four bond pads and contains the necessary routing resources to provide an interface between i/o pads and the plcs. each pic is com- posed of four programmable i/os (pios) and significant routing resources. each pio contains input buffers, output buffers, routing resources, latches/ffs, and logic and can be configured as an input, output, or bidirectional i/o. pics in the series 3 fpgas have significant local rout- ing resources, similar to routing in the plcs. this new routing increases the ability to fix user pinouts prior to placement and routing of a design and still maintain routability. the flexibility provided by the routing also provides for increased signal speed due to a greater variety of signal paths possible. included in the pic routing is a fast path from the input pins to the slics in each of the three adjacent plcs (one orthogonal and two diagonal). this feature allows for input signals to be very quickly processed by the slic decoder function and used on-chip or sent back off of the fpga. also new to the series 3 pios are latches and ffs and options for using fast, dedicated clocks called expressclks. these features will all be discussed in subsequent sections. a diagram of a single pio (one of four in a pic) is shown in figure 22. table 9 provides an overview of the programmable functions in an i/o cell. 5-5805(f).c fi g ure 22 . or3c/txxx pro g rammable in p ut/out p ut ( pio ) ima g e from orca foundr y in2 in1 d0 d1 ck sp sd lsr inregmode latchff latch ff d ck normal inverted reset set level mode ttl cmos up down none pull-mode buffer ts fast slew sink reset set lsr sp ck d out1 out2 eclk sclk ce ce_over_lsr lsr_over_ce async lsr enable_gsr disable_gsr out1outreg out2outreg out1out2 nor xor xnor and nand or pio logic clkin 0 0 1 0 pad q q 1 pd to routing q 1 eclk sclk pmux from routing mode lsr ck d0 q
lucent technologies inc. 37 data sheet june 1999 orca series 3c and 3t fpgas programmable input/output cells (continued) 5 v tolerant i/o the i/o on the or3txxx series devices allow intercon- nection to both 3.3 v and 5 v devices (selectable on a per-pin basis). the or3txxx devices will drive the pin to the 3.3 v lev- els when the output buffer is enabled. if the other device being driven by the or3txxx device has ttl- compatible inputs, then the device will not dissipate much input buffer power. this is because the or3txxx output is being driven to a higher level than the ttl level required. if the other device has a cmos-compat- ible input, the amount of input buffer power will also be small. both of these power values are dependent upon the input buffer characteristics of the other device when driven at the or3txxx output buffer voltage levels. the or3txxx device has internal programmable pull- ups on the i/o buffers. these pull-up voltages are always referenced to v dd and are always sufficient to pull the input buffer of the or3txxx device to a high state. the pin on the or3txxx device will be at a level 1.0 v below v dd (minimum of 2.0 v with a minimum v dd of 3.0 v). this voltage is sufficient to pull the exter- nal pin up to a 3.3 v cmos high input level (1.8 v, min) or a ttl high input level (2.0 v, min) in a 5 v tolerant system. therefore, in a 5 v tolerant system using 5 v cmos parts, care must be taken to evaluate the use of these pull-ups to pull the pin of the or3txxx device to a typical 5 v cmos high input level (2.2 v, min). pci compliant i/o the i/o on the or3txxx series devices allows compli- ance with pci local bus (rev. 2.2) 5 v and 3.3 v sig- naling environments. the signaling environment used for each input buffer can be selected on a per-pin basis. the selection provides the appropriate i/o clamping diodes for pci compliance. choosing an ibt input buffer will provide pci compliance in or3txxx devices. or3cxx devices have pci local bus compliant i/os for 5 v signaling. table 9. pio options in p ut o p tion input level ttl, or3cxx onl y cmos, or3cxx or or3txxx 3.3 v pci compliant, or3txxx 5 v pci compliant, or3txxx input speed fast, dela y ed float value pull-up, pull-down, none re g ister mode latch, ff, fast zero hold ff, none ( direct input ) clock sense inverted, noninverted input selection input 1, input 2, clock input out p ut o p tion output drive current 12 ma/6 ma or 6 ma/3 ma output function normal, fast open drain output speed fast, slewlim, sinklim output source ff direct-out, general routin g output sense active-hi g h, active-low 3-state sense active-hi g h, active-low ( 3-state ) ff clockin g expressclk , s y stem clock clock sense inverted, noninverted lo g ic options see table 10. i/o controls o p tion clock enable active-hi g h, active-low, alwa y s enabled set/reset level active-hi g h, active-low, no local reset set/reset t y pe s y nchronous, as y nchronous set/reset priorit y ce over lsr, lsr over ce gsr control enable gsr, disable gsr
38 38 lucent technologies inc. data sheet june 1999 orca series 3c and 3t fpgas programmable input/output cells (continued) inputs as outlined earlier in table 9, there are six major options on the pio inputs that can be selected in the orca foundry tools. for or3cxx devices, the inputs and bidirectional buffers can be configured as either ttl or cmos compatible. or3txxx devices support cmos levels only for input or bidirectional buffers, have 5 v tolerant i/os as previously explained, but can optionally be selected on a pin-by-pin basis to be pci bus 3.3 v signaling compliant (pci bus 5 v signaling compliance occurs in 5 v tolerant operation). the default buffer upon powerup for the unused sites is 5 v tolerant/5 v pci compliant. consult the orca macro library, series 3 i/o cells, for the appropriate buffers. inputs may have a pull-up or pull-down resistor selected on an input for signal stabilization and power management. input signals in a pio can be passed to pic routing on any of three paths, two general signal paths into pic routing, and/or a fast route into the clock routing system. there is also a programmable delay available on the input. when enabled, this delay affects the in1 and in2 signals of each pio, but not the clock input. the delay allows any signal to have a guaranteed zero hold time when input. this feature is discussed subsequently. inputs should have transition times of less than 500 ns and should not be left floating. if any pin is not used, it is 3-stated with an internal pull-up resistor enabled automatically after configuration. warning : during configuration, all or3txxx inputs have internal pull-ups enabled. if these inputs are driven to 5 v, they will draw substantial current ( @ 5 ma). this is due to the fact that the inputs are pulled up to 3 v. floating inputs increase power consumption, produce oscillations, and increase system noise. the or3cxx inputs have a typical hysteresis of approximately 280 mv (200 mv for the or3txxx) to reduce sensitivity to input noise. the pic contains input circuitry which pro- vides protection against latch-up and electrostatic dis- charge. the other features of the pio inputs relate to the new latch/ff structure in the input path. as shown in figure 23, the input is optionally passed to a register or latch/register pair. these structures can operate in the modes listed in table 9. in latch mode, the input signal is fed to a latch that is clocked by a system clock signal. the clock may be inverted or noninverted from its sense in the pic routing. there is also a local set/reset signal to the latch from the pic routing. the senses of these signals are also programmable as well as the capability to enable or disable the global set/reset sig- nal and select the set/reset priority. the same control signals may also be used to control the input latch/ff when it is configured as a ff instead of a latch, with the addition of another control signal used as a clock enable.
lucent technologies inc. 39 data sheet june 1999 orca series 3c and 3t fpgas programmable input/output cells (continued) zero-hold in p ut there are two options for zero-hold input capture in the pio. if input delay mode is selected to delay the signal from the input pin, data can be either registered or latched with guaranteed zero-hold time in the pio using a system clock. to guarantee zero hold, the system clock spine structure must be used for clocking, as will be discussed later. the fast zero-hold mode of the pio input takes advantage of the latch/ff combination and sources the input ff data from a dedicated latch that is clocked by the expressclk from the pic. the expressclk is a clock from a dedi- cated input pin designed for fast, low-skew operation at the i/os and is described more fully in the clock distribu- tion network and pic interquad (mid) routing sections that follow. the combination of expressclk latch and system clock ff guarantees a zero-hold capture of input data in the pio ff, while at the same time reducing input setup time. figure 23 shows a schematic of the fast-capture latch/ff and a sample timing diagram. 5-5974(f) note: ce and lsr signals not shown. figure 23. fast-capture latch and timing d q input data latch clk o i expressclk o i system clk cd = 1 clock enable local set/reset dq ff s/r ce data out to pic routing expressclk system clk input data q latch q ff b acde b acde abcd
40 lucent technologies inc. data sheet june 1999 orca series 3c and 3t fpgas programmable input/output cells (continued) in p ut demulti p lexin g the combination of input register capability and the two inputs, in1 and in2, from each pio to the internal routing provides for input signal demultiplexing without any additional resources. figure 24 shows the input configuration and general timing for demultiplexing a multiplexed address and data signal. the pio input signal is sent to both the input latch and directly to in2. the signal is latched on the falling edge of the clock and output to routing at in1. the address and data are then both available at the rising edge of the system clock. these signals may be regis- tered or otherwise processed in the plcs at that clock edge. figure 24 also shows the possible use of the slic decoder to perform an address decode to enable which registers are to receive the input data. although the timing shown is for using the input register as a latch, it may also be used in the same way as an ff. also note that the sig- nals found in pio inputs in1 and in2 can be interchanged. 5-5798(f) figure 24. pio input demultiplexing dec dq pad pio dq ce slic other address lines sclk in1 in2 sclk pio latch plc ff addr1 addr2 addr3 addr4 addr5 data1 data2 data3 data4 data1 data2 data3 addr2 addr3 addr4 addr5 data0 data4 output output pio input plc
lucent technologies inc. 41 data sheet june 1999 orca series 3c and 3t fpgas programmable input/output cells (continued) outputs the pics output drivers have programmable drive capability and slew rates. three propagation delays (fast, slewlim, sinklim) are available on output drivers. the sinklim mode has the longest propagation delay and is used to minimize system noise and minimize power consumption. the fast and slewlim modes allow critical timing to be met. the drive current is 12 ma sink/6 ma source for the slewlim and fast output speed selections and 6 ma sink/3 ma source for the sinklim output. two adja- cent outputs can be interconnected to increase the out- put sink/source current to 24 ma/12 ma. all outputs that are not speed critical should be config- ured as sinklim to minimize power and noise. the num- ber of outputs that switch simultaneously in the same direction should be limited to minimize ground bounce. to minimize ground bounce problems, locate heavily loaded output buffers near the ground pads. ground bounce is generally a function of the driving circuits, traces on the printed-circuit board, and loads and is best determined with a circuit simulation. at powerup, the output drivers are in slewlim mode, and the input buffers are configured as ttl-level com- patible (cmos for or3txxx) with a pull-up. if an output is not to be driven in the selected configuration mode, it is 3-stated. the output buffer si g nal can be inverted, and the 3-state control signal can be made active-high, active- low, or always enabled. in addition, this 3-state signal can be registered or nonregistered. additionally, there is a fast, open-drain output option that directly connects the output signal to the 3-state control, allowing the out- put buffer to either drive to a logic 0 or 3-state, but never to drive to a logic 1. because there is no explicit route required to create the open-drain output, its response is very fast. like the input side of the pio, there are two output connections from pic routing to the output side of the pio, out1, and out2. these connections provide for flexible routing and can be used in data manipulation in the pio as described in subsequent paragraphs. an ff has been added to the output path of the pio. the register has a local set/reset and clock enable. the lsr has the option to be synchronous or asynchro- nous and have priority set as clock enable over lsr or lsr over clock enable. clocking to the output ff can come from either the system clock or the expressclk associated with the pic. the input to the ff can come from either out1 or out2, or it can be tied to v dd or gnd. additionally, the input to the ff can be inverted. out p ut multi p lexin g the series 3 pio output ff can be combined with the new pio logic block to perform output data multiplexing with no plc resources required. the pio logic block has three multiplexing modes: out1outreg, out2outreg, and out1out2. out1outreg and out2outreg are equivalent except that either out1 or out2 is muxed with the ff, where the ff data is output on the clock phase after the active edge. the simplest multiplexing mode is out1out2. in this mode, the signal at out1 is output to the pad while the clock is low, and the signal on out2 is output to the pad when the clock is high. figure 25 shows a simple schematic of a pio in out1out2 mode and a general timing diagram for multiplexing an address and data signal. often an address will be used to generate or read a data sample from memory with the goal of multiplexing the data onto a single line. in this case, the address often precedes the data by one clock cycle. out1outreg and out2outreg modes of the pio logic can be used to address this situation. because out1outreg mode is equivalent to out2outreg, only out2outreg mode is described here. figure 26 shows a simple pio sche- matic in out2outreg mode and general timing for multiplexing data with a leading address. the address signal on out1 is registered in the pio ff. this delays the address so that it aligns with the data signal. the pio logic block then sends the outreg signal (address) to the pad when the clock is high and the out2 signal (data) to the pad when the clock is low, resulting in an aligned, multiplexed signal.
42 lucent technologies inc. data sheet june 1999 orca series 3c and 3t fpgas programmable input/output cells (continued) note: pio logic mode, out1out2 5-5799(f) figure 25. output multiplexing (out1out2 mode) note: pio logic mode, out1out2 5-5797(f) figure 26. output multiplexing (out2outreg mode) clk addr1 addr2 addr3 addr4 addr5 data2 data3 data4 data5 addr1 addr2 addr3 data1 data2 data3 data4 data1 addr4 out1 out2 pic output plc address pad pio logic out1 out2 clk from routing data from routing pic plc dq clk pad p/o logic out1 out2 pic data clk reg address data addr1 addr2 addr3 addr4 data1 data2 data3 data4 data1 data2 addr1 addr2 addr3 addr4 data3 pad addr addr1 addr2 addr3 addr4 addr5 from routing address from routing
lucent technologies inc. 43 data sheet june 1999 orca series 3c and 3t fpgas pro g rammable in p ut/out p ut cells ( continued ) pio lo g ic function generator the pio logic block can also generate logic functions based on the signals on the out2 and clk ports of the pio. the functions are and, nand, or, nor, xor, and xnor. table 10 is provided as a summary of the pio logic options. pio register control signals as discussed in the inputs and outputs subsections, the pio latches/ffs have various clock, clock enable (ce), local set/reset (lsr), and global set/reset (gsrn) controls. table 11 provides a summary of these control signals and their effect on the pio latches/ffs. note that all control signals are optionally invertible. table 10. pio logic options o p tion descri p tion out1outreg data at out1 output when clock low, data at ff out when clock hi g h. out2outreg data at out2 output when clock low, data at ff out when clock hi g h. out1out2 data at out1 output when clock low, data at out2 when clock hi g h. and output lo g ical and of si g nals on out2 and clock. nand output lo g ical nand of si g nals on out2 and clock. or output lo g ical or of si g nals on out2 and clock. nor output lo g ical nor of si g nals on out2 and clock. xor output lo g ical xor of si g nals on out2 and clock. xnor output lo g ical xnor of si g nals on out2 and clock. table 11. pio register control signals control si g nal effect/functionalit y expressclk clocks input fast-capture latch; optionall y clocks output ff, or 3-state ff. s y stem clock ( sclk ) clocks input latch/ff; optionall y clocks output ff, or 3-state ff. clock enable ( ce ) optionall y enables/disables input ff ( not available for input latch mode ) ; optionall y enables/dis- ables output ff; separate ce inversion capabilit y for input and output. local set/reset ( lsr ) option to disable; affects input latch/ff, output ff, and 3-state ff if enabled. global set/reset ( gsrn ) option to enable or disable per pio after initial confi g uration. set/reset mode the input latch/ff, output ff, and 3-state ff are individuall y set or reset b y both the lsr and gsrn inputs.
44 44 lucent technologies inc. data sheet june 1999 orca series 3c and 3t fpgas programmable input/output cells (continued) pic routing resources the pic routing borrows many of the concepts and constructs from the plc routing. it is designed to be able to gather an 8-bit bidirectional bus from any eight consecutive i/o pads and route them to either or both of the two adjacent plcs. the eight i/o bits do not need to start at a pic boundary; that is, they may start at one of the middle two pios in a pic and span three pics. substantial routing has been added to the pic to off- load plc routing from being used to move signals around the plc array perimeter. this saves plc rout- ing for logic purposes and provides greater flexibility for locking design pinouts prior to final placement and rout- ing of the device, or allowing a change in the pinout late in the design cycle. the pic routing has also been increased substantially to allow routing to the complex pio cells that now allow multiple inputs and outputs per device pin, along with new sequential control signals, such as clock enable, lsr, and clock. pics are grouped in pairs for purposes of discussing pic routing. on the sides of a device, the pics in a pair are referred to as top and bottom. on the top or bottom of a device, the pics in a pair are referred to as left or right. for example, on the top edge of the device, the leftmost pic, pt1, is the left pic of a pair, and pic pt2 is the right pic of that pair. the next pic to the right, pt3, is the left pic of the next pair, and so on. the need for pic pairs stems from the routing of switching segments and plc half- and long-line driv- ers. as described below, the connectivity for these types of routing is grouped across pairs of pics to pro- vide complete and fast routing of i/o signals between a given pic and the three adjacent plcs: one orthogonal and two diagonal. pic routing segments use the same terminology as plc routing segments, but are prefixed with a p to dis- tinguish them as belonging to the pics. pic switching segments. each pic has two groups of switching segments (psw), each group having eight lines with connectivity to the pios in groups of four. one set of switching segments connects to the pic to the left (above), and the other set connects to the switching segments of the pic to the right (below). this means of connectivity between pics using staggered connections of groups of switching segments allows a given pic to route signals to both adjacent pics and all adjacent plcs efficiently. this provides single signal routing flexibility and routing of multiple buses on groups of i/os without tying up global routing resources. px1 routing segments. there are five px1 routing segments in each pic that run parallel to the edge of the chip on which the pic resides, each broken by a cip in each pic. the px1 segments have connectivity to the psw segments and to the x1 routing segments of the two adjacent plcs. px2 routing segments. there are five px2 routing segments in each pic that run parallel to the edge of the chip on which the pic resides. to provide greater routing flexibility, the cips that break the px2 segments every two pics are staggered across the two pics in a pair. one pic of the pair has break cips on the even- numbered px2 segments, and the other has them on the odd-numbered px2 segments. the px2 segments have connectivity to the psw segments and to the x1 routing segments of the two adjacent plcs. px5 routing segments. there are ten px5 routing segments in each pic that run parallel to the edge of the chip on which the pic resides. two of the ten seg- ments are broken in each pic so that each segment is broken every five pics. all ten px5 segments break at the corners of the chip, allowing independent px5 rout- ing on each edge of the chip. the px5 routing seg- ments connect to the psw segments and the x5 and xh routing segments of the two adjacent plcs. pxh routing segments. each pic contains eight pxh routing segments that run parallel to the edge of the chip on which the pic resides. the pxh segments have connectivity with the xl, xh, and one set of xbid rout- ing segments in the immediately adjacent plc. pxl routing segments. there are ten pxl routing segments in each pic that run parallel to the edge of the chip on which the pic resides. each of the xl lines makes a connection to an xl line from the adjacent plc. pic long lines (xl) can be used for global signal distribution just as plc xl lines can.
lucent technologies inc. 45 data sheet june 1999 orca series 3c and 3t fpgas programmable input/output cells (continued) pic architectural description the pic architecture as seen in orca foundry is shown in figure 27. the figure is the left pic of a pic pair on the top edge of a series 3 array. both pics in a pair are similar, with the differences mainly lying in the connections between the pic switching segments (psw), the in2 connections across pic boundaries, and the system clock spine driver residing in only one pic of a pair. a . this is a pro g rammable input/output ( pio ) . there are four pios per pic. the pios contain the pic lo g ic and i/o buffers. b . this is the pic output switchin g block. it connects the pic switchin g se g ments and local clock lines to the pio output and control si g nals. c . this is the s y stem clock spine switchin g block and buffer. there is onl y one s y stem clock spine per pair of pics. its inputs can come from the pic switchin g se g ments or an y of the ei g ht pio inputs in a pic pair. d .pic switchin g se g ments ( psw ) . these routin g se g - ments are used to interconnect routin g resources within the pic and to a lesser de g ree, between pics. e . px1 routin g se g ments. the pic x1 routin g se g - ments traverse one pic and break at a cip in the middle of each pic. f . px2 routin g se g ments. the pics have routin g that traverses two pics between breaks. the breaks are sta gg ered amon g the five px2 se g ments. g . px5 routin g se g ments. each of the ten pic x5 rout- in g se g ments traverses five pics in between breaks at a cip. two px5 se g ments break in each pic. h . pxh routin g se g ments. the ei g ht pic xh routin g se g ments traverse half of the arra y and break at cips in the inter q uad routin g re g ion that is in the middle of the arra y . i . ( not used intentionall y for clarit y . ) j . pxl routin g se g ments. the pic lon g lines run the entire len g th of the side of the arra y . k .x5 routin g se g ments from the ad j acent plc routin g . l .xl routin g se g ments from the ad j acent plc routin g . m .x1 routin g se g ments from the ad j acent plc routin g . n .switchin g se g ments from the ad j acent plc routin g . o .xh routin g se g ments from the ad j acent plc routin g . p . bidi routin g se g ments from the ad j acent plc rout- in g . q . these are the in2 routin g se g ments. there is one in2 line from each pio, and all ei g ht in2 lines from each pic pair are present in both pics of a pair. r . these cips connect the in1 and in2 routin g se g - ments from the pios to the pic switchin g se g - ments. s . these cips break the pic switchin g se g ments at the interface between a pic pair. t . these cips connect ad j acent plc routin g resources to the pic switchin g se g ments. u . these cips connect inter-pic routin g with the pic switchin g se g ments. v . these cips break the px1, px2, and px5 routin g at the middle of a pic. the px2 and px5 cip place- ment varies dependin g on the plc. w . these mutuall y exclusive buffers can drive one lon g line si g nal onto a pic local clock routin g se g ment. x . these mutuall y exclusive buffers can select a source from one of the local s y stem clock routes to drive the pio 3-state control si g nal. y . these are the four local s y stem clock routin g se g - ments. two come from connections within the pic, one from the other pic in the pair, and one from the ad j acent plc. z . these mutuall y exclusive buffers allow a si g nal on the pic switchin g se g ments to be routed to a s y s- tem clock spine or to a pio s y stem clock. aa . expressclk routin g line. ab .s y stem clock spine. ac . these various g roups of cips connect routin g resources from the ad j acent plc to the inter-pic routin g resources. ad . these buffers provide connectivit y between the plc xl ( xh ) lines and the pic xl ( xh ) lines or connectivit y between one of the in2 routin g se g - ments and the pic and/or plc xl ( xh ) routin g se g ments. ae . these mutuall y exclusive buffers and cips provide connectivit y to the plc xl and xh lines from one of the in2 input se g ments. af . these buffers allow the in2 si g nals to drive onto the bidi routin g of the ad j acent plc, or the bidi routin g of the ad j acent plc, and the pic switchin g se g ments and/or pic half lines ma y be connected.
46 lucent technologies inc. data sheet june 1999 orca series 3c and 3t fpgas programmable input/output cells (continued) 5-5823(f) figure 27. pic architecture aa aa aa b y d d d d e f h j z x ac g ae ad t w r t v u u ac j q q r r c p o n m ad m k l k s af w t h ae ac ab
lucent technologies inc. 47 data sheet june 1999 orca series 3c and 3t fpgas high-level routing resources the high-level routing resources in the orca series 3 devices are interquad routing, corner cell routing, and pic interquad routing. these resources and their related structures are discussed in the following subsections. interquad routing in the orca series 3 devices, the plc array is split into four equal quadrants. in between these quadrants, routing has been added to route signals between the quadrants and distribute clocks. in addition to general routing, there are four specialized clock routing spines. the general routing is discussed below, followed by the special clock rout- ing. one of the main purposes of interquad routing is to distribute internally generated signals, such as clocks and con- trol signals. there are two types of interquad blocks: vertical and horizontal. vertical interquad blocks (viq) run between quadrants on the left and right, while horizontal interquad blocks (hiq) run between top and bottom quad- rants. interquad lines begin and end in the mid cells that are discussed later. since hiq and viq blocks have the same logic, only the hiq block is described below. the interquad routing connects to x5 and xh segments. it does not affect other local routing (xsw, x1, fast carry), so local routing is the same, whether plc-plc connections cross quadrants or not. figure 28 presents a (not to scale) view of interquad routing. 5-4538(f) fi g ure 28. inter q uad routin g tmid bmid 5 5 5 5 viq2[4:0] viq4[4:0] viq6[4:0] viq8[4:0] viq0[4:0] viq3[4:0] viq5[4:0] viq7[4:0] viq9[4:0] viq1[4:0] 5 5 5 5 5 5 lmid rmid hiq7[4:0] hiq5[4:0] hiq3[4:0] hiq1[4:0] hiq9[4:0] hiq6[4:0] hiq4[4:0] hiq2[4:0] hiq0[4:0] hiq8[4:0] 5 5 5 5 5 5 5 5 5 5 fast clock r fast clock l fast clock t fast clock b
48 48 lucent technologies inc. data sheet june 1999 orca series 3c and 3t fpgas high-level routing resources (continued) figure 29 shows the connections from the interquad routing to the inter-plc routing for a block of the hori- zontal interquad. the vertical interquad has similar connections. the connections shown in figure 29 are made with plcs located above and below the routing shown in the figure. the interquad routing segments, prefixed ih for interquad horizontal, are in ten groups of five lines. any one line from each group can be routed to one of the xh segments from the top of the device (left for vertical interquad), one of the xh segments from the bottom of the device (right for vertical inter- quad), and one of the x5 segments crossing the inter- quad. figure 28 shows four fast middle clock (fast clock) sig- nals with the suffixes t (top), b (bottom), r (right), and l (left), respectively. figure 29 also shows the fast clock r and fast clock l lines; these are dedicated interquad clock spines. they originate in the clkcn- trl special function blocks in the middle of each edge of the device, with the name referencing the edge of origin. for example, fast clock r originates in the clkcntrl block on the right edge of a device. fast clock spines traverse the entire plc array but do not connect to the pics on the edge of the device opposite to the source. each fast clock line connects to two of the xl lines in each plc that run orthogonally to the fast clock. these connections allow the fast clock lines to generate a clock tree that can reach any plc in the device. fast clocks and other clock resources are dis- cussed in the clock distribution network section. programmable corner cell routing pro g rammable routin g the programmable corner cell (pcc) contains the cir- cuitry to connect the routing of the two pics in each corner of the device. the pic px1 and px2 segments and eight pic switching segments are directly con- nected together from one pic to another. the px5 lines are all broken with cips and the pic pxl and pxh segments are connected from one block to another through programmable buffers. corner cell s p ecial functions in addition to routing functions, special-purpose func- tions are located in each fpga corner. the upper-left pcc contains connections to the boundary-scan logic and microprocessor interface. the upper-right pcc contains connections to the readback logic, connectiv- ity to the global 3-state signal (ts_all), and a pro- grammable clock manager. the lower-left pcc contains connections to the internal oscillator and a programmable clock manager. the lower-right pcc contains connections to the start-up and global reset logic. these functions are all more completely described in the special function blocks section of this data sheet. 5-5821(f) figure 29. hiq block detail ih0[4:0] ih1[4:0] ih2[4:0] ih3[4:0] ih4[4:0] fast clock r ih5[4:0] ih6[4:0] ih7[4:0] ih8[4:0] ih9[4:0] fast clock l bl[9:0] vxl[9:0] vx5[9:0] vx1[9:0] sul[9:0] vx1[9:0] vxh[9:0] bl[9:0] fast vck carry
lucent technologies inc. 49 data sheet june 1999 orca series 3c and 3t fpgas high-level routing resources (continued) pic interquad (mid) routing there is also connectivity between the pics in each quadrant, as well as a clock control (clkcntrl) mod- ule (discussed in the special function blocks section) between the pic routing and the interquad routing. these blocks are called lmid (left), tmid (top), rmid (right), and bmid (bottom). the tmid routing is shown in figure 30. as with the hiq and viq blocks, the only connectivity to the pic routing is to the global pxh and px5 segments. the pxh segments from the one quadrant can be con- nected through a cip to its counterpart in the opposite quadrant, providing a path that spans the array of pics. since a passive cip is used to connect the two pxh segments, a 3-state signal can be routed on the two pxh segments in the opposite quadrants, and then connected through this cip. as with the hiq and viq blocks, cips and buffers allow nibble-wide connections between the interquad segments, the xh segments, and the x5 segments. 5-5822(f) figure 30. top (tmid) routing expressclk right pic local clocks pic local clocks pxl[9:0] pxh[7:0] px5[9:0] px1[4:0] psw[7:4] psw[3:0] psw[7:4] psw[3:0] px2[4:0] 1v9xl[4] 1v8xl[3] iv7xl[2] fast clock iv7xl[0] iv6xl[3] iv6xl[1] iv5xl[2] iv5xl[0] iv4xl[3] iv3xl[3] iv3xl[1] iv2xl[2] iv2xl[0] iv1xl[3] iv1xl[1] 1v0xl[2] 1v0xl[0] iv4xl1] in2[a:d] from left in[a:d] from right corner expressclk from right from left expressclk left shutoff
50 50 lucent technologies inc. data sheet june 1999 orca series 3c and 3t fpgas clock distribution network the series 3 fpgas provide three types of high- speed, low-skew clock distributions: system clock, fast middle clock (fast clock), and expressclk . because of the great variety of sources and distribution for clock signals in the orca series 3, the clock mechanisms will be described here from the inside out. the clock connections to the pfu will be described, followed by clock distribution to the plc array, clock sources to the plc array, and finally ending with clock sources and distribution in the pics. the expressclk inputs are new, dedicated clock inputs in series 3 fpgas. they are mentioned in several of the clock network descrip- tions and are described fully later in this section. pfu clock sources within a plc there are five sources for the clock signal of the latches/ffs in the pfu. two of the signals are generated off of the long lines (xl) within the plc: one from the set of vertical long lines and one from the set of horizontal long lines. for each of these signals, any one of the ten long lines of each set, vertical or horizon- tal, can generate the clock signal. two of the five pfu clock sources come from neighboring plcs. one clock is generated from the plc to the left or right of the cur- rent plc, and one is generated from the plc above or below the current plc. the selection decision as to where these signals come from, above/below and left/ right, is based on the position of the plc in the array and has to do with the alternating nature of the source of the system clock spines (discussed later). the last of the five clock sources is also generated within the plc. the e1 control signal, described in the plc routing resources section, can drive the pfu clock. the e1 signal can come from any xbid routing resource in the plc. the selection and switching of clock signals in a plc is performed in the fins . figure 31 shows the pfu clock sources for a set of four adjacent plcs. global control si g nals the four clock signals in each plc that are generated from the long lines (xl) in the current plc or an adja- cent plc can also be used to drive the pfu clock enable (ce), local set/reset (lsr) and add/subtract/ write enable (aswe) signals. the clock signals gener- ated from vertical long lines can drive ce and aswe, and the clocks generated from horizontal long lines can drive lsr. this allows for low-skew global distribution of two of these three control signals with the clock rout- ing while still allowing a global clock route to occur. 5-6054(f) figure 31. pfu clock sources pfu plc pfu plc pfu plc pfu plc e1 e1 e1 e1 hxl[9:0] hxl[9:0] vxl[9:0] vxl[9:0]
lucent technologies inc. 51 data sheet june 1999 orca series 3c and 3t fpgas clock distribution network (continued) clock distribution in the plc array s y stem clock ( sclk ) the clock distribution network, or clock spine network, within the plc array is designed to minimize clock skew while maximizing clock flexibility. clock flexibility is expressed in two ways: the ease with which a single clock is routed to the entire array, and the capability to provide multiple clocks to the plc array. there is one horizontal and one vertical clock spine passing through each plc. the horizontal clock spine is sourced from the pic in the same row on either the left- or right-hand side of the array, with the source side (left or right) alternating for each row. the vertical clock spines are similarly sourced from the pics alternating from the top or bottom of a column. each clock spine is capable of driving one of the ten xl routing segments that run orthogonal to it within each plc. full connec- tivity to all pfus is maintained due to the connectivity from the xl lines to the pfu clock signals described in the previous section; however, only an xl line in every other row (column) needs to be driven to allow the given clock signal to be distributed to every pfu. figure 32 is a high-level diagram of the series 3 system clock spine network with sample xl line connections for a 4 x 4 array of plcs. the clock spine structure previously described pro- vides for complete distribution of a clock from any i/o pin to the entire plc array by means of a single clock spine and long lines (xl). this distribution system also provides a means to have many different clocks routed to many different and dispersed locations in the plc array. each spine can carry a different clock signal, so for the or3c/t55 (which has an 18 x 18 array of plcs, implying nine clock spines per side), 36 input clock sig- nals can be supported using the system clock network. fast clock fast clocks are high-speed, low-skew clock spines that originate from the clkcntrl special function blocks (described later). there are four fast clock spinesone originating on the middle of each edge of the array. the spines run in the interquad region of the plc array from their source side of the device to the last row or column on the opposite side of the device. the fast clocks connect to two long lines, xl[8] and xl[9], that run orthogonal to the spine direction in each plc. these long lines can then be connected to the pfu clock input in the same manner as the general system clocks, and, like the system clock connections, xl lines are only needed in every other row (column) to distrib- ute a clock to every pfu. the limited number of long- line connections and the low skew of the clkcntrl source combine to make the fast clocks a very robust, low-skew clock source. 5-5801(f).a figure 32. orca series 3 system clock distribution overview (xl) horizontal (xl) unused (xl) (xl) unused sclk spine (xl) unused sclk spine vertical sclk spine sclk spine sclk spine unused sclk spine unused sclk spine unused sclk spine unused sclk spine unused sclk spine
52 52 lucent technologies inc. data sheet june 1999 orca series 3c and 3t fpgas clock distribution network (continued) clock sources to the plc array the source of a clock that is globally available to the plc array can be from any user i/o pad, any of the expressclk pads, or an internally generated source. s y stem clock as described in the programmable input/output cells section, pics are grouped in adjacent pairs. any one of the eight pads in a pic pair can drive a clock spine in a row or column. for pic pairs on the top of the chip, the column associated with the left pic has the clock spine, for pairs on the bottom, the right pic column has the spine. the top pic of the pair sources the spine from the left side of the array, and the bottom pic of the pair sources the spine from the right side of the array. clock delay and skew are minimized by having a single clock buffer per pair of pics. the clock spine for each pair can also be driven by one of the four pic switching segments (psw) in each pic of the pair. this allows a signal generated in the plc array to be routed onto the global clock spine network. the system clock output of the programmable clock manager ( pcm ) may also be routed to the global system clock spines via the psw segments. figure 33 shows the clock spine multiplex- ing structure for a pair of pics on the top of the array. fast clock the fast clock spines are sourced to the plc array from each side of the device by the expressclk pads via the clkcntrl function block (described in the special function blocks section). the expressclk and fast clock source from the pads is shown in figure 34 and will be described further in the expressclk inputs subsection. 5-5800(f) figure 33. pic system clock spine generation clocks in the pics because the series 3 fpgas have latches and ffs in the i/os, it is necessary to have clock signal distribution to the pios as well as in the plc array. the system clock, the fast clock, and the expressclk are available for pio clocking. pic system clock there are five local system clock lines in each pic. much like the sources for a clock in the pfu, two of the local pic clocks are generated within the pic from long lines. one is generated from the set of ten pic long lines (pxl) that runs parallel to the pics on a side, and the other is generated from the set of ten long lines (xl) from the plc array that terminate in the pic. another local pic system clock route comes from the set of ten xl lines in the adjacent plc that is parallel to the side of the array on which the pic resides. the fourth local pic system clock route comes from the set of ten long lines (xl) from the plc array that terminate in the adja- cent pic that is not part of the same pic pair. much like the e1 signals in the plcs that are used to distribute a local clock to the pfu source, the fifth local clock line in each pic comes from local psw signals. this clock signal for each pic is shown in figure 33. one of these five local pic system clocks is selected for the system clock signal in the pio. it is used as the pio system clock for both input and output clocking as selected within the pio. all pios in a pic share the same sys- tem clock. pic expressclk the expressclk signal used at the pic latches/ffs comes from the clkcntrl function block that resides in the middle of the side on which the pic resides. a single signal comes from the clkcntrl and is driven by separate buffers onto two expressclk long wires. one of these expressclk signals goes to the pics on the right of (above) the clkcntrl block, and the other expressclk signal goes to the pics on the left of (below) the clkcntrl block on that side. pad a pad b pad c pad d psw[4] psw[5] psw[6] psw[7] pad a pad b pad c pad d psw[4] psw[5] psw[6] psw[7] spine to local clocks to local clocks tpicl tpicr
lucent technologies inc. 53 data sheet june 1999 orca series 3c and 3t fpgas clock distribution network (continued) expressclk inputs there are four dedicated expressclk pads on each series 3 device: one in the middle of each side. two other user i/o pads can also be used as corner expressclk inputs, one on the lower-left corner, and one on the upper-right corner. the corner expressclk pads feed the expressclk to the two sides of the array that are adjacent to that corner, always driving the same signal in both directions. the expressclk route from the middle pad and from the corner pad associ- ated with that side are multiplexed and can be glitch- lessly stopped/started under user control using the stopclk feature of the clkcntrl function block (described under special function blocks) on that side. the expressclk output of the programmable clock manager ( pcm ) is programmably connected to the cor- ner expressclk routes. pcm blocks are found in the same corners as the corner expressclk signals and are described in the special function blocks section. the expressclk structure is shown in figure 34 ( pcm blocks are not shown). 5-5802(f) note: all multiplexers are set durin g confi g uration. figure 34. expressclk and fast clock distribution selecting clock input pins any user i/o pin on an orca fpga can be used as a fast, low-skew system clock input. since the four dedi- cated expressclk inputs can only be used to distribute global signals into the fpga, these pins should be selected first as clock pins. within the interquad region of the device, these clocks sourced by the expressclk inputs are called fast clocks. choosing the next clock pin is completely arbitrary, but using a pin that is near the center of an edge of the device will provide the low- est skew system clock network. the pin-to-pin timing numbers in the timing characteristics section assume that the clock pin is in one of the pics at the center of any side of the device next to an expressclk pad. for actual timing characteristics for a given clock pin, use the timing analyzer results from orca foundry. to select subsequent clock pins, certain rules should be followed. as discussed in the programmable input/ output cells section, pics are grouped into adjacent pairs. each of these pairs contains eight i/os, but only one of the eight i/os in a pic pair can be routed directly onto a system clock spine. therefore, to achieve top performance, the next clock input chosen should not be one of the pins from a pic pair previously used for a clock input. if it is necessary to have a second input in the same pic pair route onto global system clock rout- ing, the input can be routed to a free clock spine using the pic switching segment (psw) connections to the clock spine network at some small sacrifice in speed. alternatively, if global distribution of the secondary clock is not required, the signal can be routed on long lines (xl) and input to the pfu clock input without using a clock spine. another rule for choosing clock pins has to do with the alternating nature of clock spine connections to the xl and pxl routing segments. starting at the left side of the device, the first vertical clock spine from the top connects to hxl[0] (horizontal xl[0]), and the first verti- cal clock spine from the bottom connects to hxl[5] in all plc rows. the next vertical clock spine from the top connects to hxl[1], and the next one from the bottom connects to hxl[6]. this progression continues across the device, and after a spine connects to hxl[9], the next spine connects to hxl[0] again. similar connec- tions are made from horizontal clock spines to vxl (ver- tical xl) lines from the top to the bottom of the device. because the orca series 3 clock routing only requires the use of an xl line in every other row or col- umn, even two inputs chosen 20 plcs apart on the same xl line will not conflict, but it is always better to avoid these choices, if possible. the fast clock spines in the interquad routing region also connect to xl[8] and xl[9] for each set of xl lines, so it is better to avoid user i/os that connect to xl[8] or xl[9] when a fast clock is used that might share one of these connec- tions. another reason to use the fast clock spines is that since they use only the xl[9:8] lines, they will not conflict with internal data buses which typically use xl[7:0]. for more details on clock selection, refer to application notes on clock distribution in orca series 3 devices. expressclks to pios fast clocks expressclk pads clkcntrl block
54 54 lucent technologies inc. data sheet june 1999 orca series 3c and 3t fpgas special function blocks special function blocks in the series 3 provide extra capabilities beyond general fpga operation. these blocks reside in the corners and mids (middle inter- quad areas) of the fpga array. single function blocks most of the special function blocks perform a specific dedicated function. these functions are data/configura- tion readback control, global 3-state control (ts_all), internal oscillator generation, global set/reset (gsrn), and start-up logic. readback logic the readback logic is located in the upper right corner of the fpga and can be enabled via a bit stream option or by instantiation of a library readback component. readback is used to read back the configuration data and, optionally, the state of the pfu outputs. a read- back operation can be done while the fpga is in nor- mal system operation. the readback operation cannot be daisy-chained. to use readback, the user selects options in the bit stream generator in the orca foundry development system. table 12 provides readback options selected in the bit stream generator tool. the table provides the number of times that the configuration data can be read back. this is intended primarily to give the user control over the security of the fpgas configuration program. the user can prohibit readback (0), allow a single readback (1), or allow unrestricted readback (u). readback can be performed via the series 3 micropro- cessor interface ( mpi ) or by using dedicated fpga readback controls. if the mpi is enabled, readback via the dedicated fpga readback logic is disabled. read- back using the mpi is discussed in the microprocessor interface ( mpi ) section. the pins used for dedicated readback are readback data (rd_data), read configuration ( rd_cfg ), and configuration clock (cclk). a readback operation is ini- tiated by a high-to-low transition on rd_cfg . the rd_cfg input must remain low during the readback operation. the readback operation can be restarted at frame 0 by driving the rd_cfg pin high, applying at least two rising edges of cclk, and then driving rd_cfg low again. one bit of data is shifted out on rd_data at the rising edge of cclk. the first start bit of the readback frame is transmitted out several cycles after the first rising edge of cclk after rd_cfg is input low (see the readback timing characteristics table in the timing characteristics section). to be certain of the start of the readback frame, the data can be monitored for the 01 frame start bit pair. readback can be initiated at an address other than frame 0 via the new microprocessor interface ( mpi ) control registers (see the microprocessor interface ( mpi ) section for more information). in all cases, read- back is performed at sequential addresses from the start address. it should be noted that the rd_data output pin is also used as the dedicated boundary-scan output pin, tdo. if this pin is being used as tdo, the rd_data output from readback can be routed internally to any other pin desired. the rd_cfg input pin is also used to control the global 3-state (ts_all) function. before and during configuration, the ts_all signal is always driven by the rd_cfg input and readback is disabled. after con- figuration, the selection as to whether this input drives the readback or global 3-state function is determined by a set of bit stream options. if used as the rd_cfg input for readback, the internal ts_all input can be routed internally to be driven by any input pin. table 12. readback options o p tion function 0 prohibit readback 1 allow one readback onl y u allow unrestricted number of readbacks
lucent technologies inc. 55 data sheet june 1999 orca series 3c and 3t fpgas special function blocks (continued) the readback frame contains the configuration data and the state of the internal logic. during readback, the value of all registered pfu and pic outputs can be captured. the following options are allowed when doing a capture of the pfu outputs. 1. do not capture data ( the data written to the rams, usuall y 0, will be read back ) . 2. capture data upon enterin g readback. 3. capture data based upon a confi g urable si g nal internal to the fpga. if this si g nal is tied to lo g ic 0, capture rams are written continuousl y . 4. capture data on either options 2 or 3 above. the readback frame has an identical format to that of the configuration data frame, which is discussed later in the configuration data format section. if lut memory is not used as ram and there is no data capture, the readback data (not just the format) will be identical to the configuration data for the same frame. this eases a bitwise comparison between the configuration and readback data. the configuration header, including the length count field, is not part of the readback frame. the readback frame contains bits in locations not used in the configuration. these locations need to be masked out when comparing the configuration and readback frames. the development system optionally provides a readback bit stream to compare to readback data from the fpga. also note that if any of the luts are used as ram and new data is written to them, these bits will not have the same values as the original configuration data frame either. global 3-state control (ts_all) to increase the testability of the orca series fpgas, the global 3-state function (ts_all) disables the device. the ts_all signal is driven from either an external pin or an internal signal. before and during configuration, the ts_all signal is driven by the input pad rd_cfg . after configuration, the ts_all signal can be disabled, driven from the rd_cfg input pad, or driven by a general routing signal in the upper right cor- ner. before configuration, ts_all is active-low; after configuration, the sense of ts_all can be inverted. the following occur when ts_all is activated: 1. all of the user i/o output buffers are 3-stated, the user i/o input buffers are pulled up ( with the pull- down disabled ) , and the input buffers are confi g ured with ttl input thresholds ( or3cxx onl y) . 2. the tdo/rd_data output buffer is 3-stated. 3. the rd_cfg , reset , and prgm input buffers remain active with a pull-up. 4. the done output buffer is 3-stated, and the input buffer is pulled up. internal oscillator the internal oscillator resides in the lower left corner of the fpga array. it has output clock frequencies of 1.25 mhz and 10 mhz. the internal oscillator is the source of the internal cclk used for configuration. it may also be used after configuration as a general- purpose clock signal. global set/reset (gsrn) the gsrn logic resides in the lower right corner of the fpga. gsrn is an invertible, default, active-low signal that is used to reset all of the user-accessible latches/ ffs on the device. gsrn is automatically asserted at powerup and during configuration of the device. the timing of the release of gsrn at the end of config- uration can be programmed in the start-up logic described below. following configuration, gsrn may be connected to the reset pin via dedicated routing, or it may be connected to any signal via normal routing. within each pfu and pio, individual ffs and latches can be programmed to either be set or reset when gsrn is asserted. a new option in series 3 allows indi- vidual pfus and pios to turn off the gsrn signal to its latches/ffs after configuration. the reset input pad has a special relationship to gsrn. during configuration, the reset input pad always initiates a configuration abort, as described in the fpga states of operation section. after configura- tion, the global set/reset signal (gsrn) can either be disabled (the default), directly connected to the reset input pad, or sourced by a lower-right corner signal. if the reset input pad is not used as a global reset after configuration, this pad can be used as a normal input pad.
56 56 lucent technologies inc. data sheet june 1999 orca series 3c and 3t fpgas special function blocks (continued) start-up logic the start-up logic block is located in the lower right cor- ner of the fpga. this block can be configured to coor- dinate the relative timing of the release of gsrn, the activation of all user i/os, and the assertion of the done signal at the end of configuration. if a start-up clock is used to time these events, the start-up clock can come from cclk, or it can be routed into the start- up block using lower right corner routing resources. these signals are described in the start-up subsection of the fpga states of operation section. clock control (clkcntrl) and stopclk there is one clkcntrl block in the mid section of the interquad routing on each side of the fpga. this block is used to selectively distribute the fast clock to the plc array and the left (top) and right (bottom) expressclks (eckl and eckr) to the side of the array on which the clkcntrl block resides. the source clock for the clkcntrl block comes either from the expressclk pad at the middle of the side of the fpga or from the corner expressclk route that comes from the corner expressclk pad (at the lower left or upper right of the device, whichever is closer). the programmable clock manager expressclk output can also be sourced to this corner routing for distribution at the two closest clkcntrl blocks. each clkcntrl block also features an invertible stopclk shutoff input that is available from local rout- ing. this feature may be used to glitchlessly stop and start the clock at the three outputs of each clkcntrl block and has the option of doing so on either the rising or falling edge of the clock. when the clock is halted based on its rising edge, it stops and stays at v dd . when it is stopped based on its falling edge, it stops and stays at gnd. if the stopclk shutoff signal meets the clkcntrl setup and hold times, the clock is stopped on the second clock cycle after the shutoff sig- nal. a diagram of the bottom clkcntrl block and stopclk timing is shown in figure 35. 5-5981(f) notes: clkcntrl output clocks are expressclk left and right and fast clock. clock shutoff shown active-high acting on clock falling edge. figure 35. top clkcntrl function block corner expressclk clock shutoff expressclk right expressclk left fast clock clock shutoff off_set off_hld off_set off_hld clkcntrl output clocks
lucent technologies inc. 57 data sheet june 1999 orca series 3c and 3t fpgas special function blocks (continued) boundary scan the increasing complexity of integrated circuits (ics) and ic packages has increased the difficulty of testing printed-circuit boards (pcbs). to address this testing problem, the ieee standard 1149.1/d1 ( ieee standard test access port and boundary-scan architecture) is implemented in the orca series of fpgas. it allows users to efficiently test the interconnection between integrated circuits on a pcb as well as test the inte- grated circuit itself. the ieee 1149.1/d1 standard is a well-defined protocol that ensures interoperability among boundary-scan (bscan) equipped devices from different vendors. the ieee 1149.1/d1 standard defines a test access port (tap) that consists of a four-pin interface with an optional reset pin for boundary-scan testing of inte- grated circuits in a system. the orca series fpga provides four interface pins: test data in (tdi), test mode select (tms), test clock (tck), and test data out (tdo). the prgm pin used to reconfigure the device also resets the boundary-scan logic. the user test host serially loads test commands and test data into the fpga through these pins to drive out- puts and examine inputs. in the configuration shown in figure 36, where boundary scan is used to test ics, test data is transmitted serially into tdi of the first bscan device (u1), through tdo/tdi connections between bscan devices (u2 and u3), and out tdo of the last bscan device (u4). in this configuration, the tms and tck signals are routed to all boundary-scan ics in parallel so that all boundary-scan components operate in the same state. in other configurations, mul- tiple scan paths are used instead of a single ring. when multiple scan paths are used, each ring is indepen- dently controlled by its own tms and tck signals. figure 37 provides a system interface for components used in the boundary-scan testing of pcbs. the three major components shown are the test host, boundary- scan support circuit, and the devices under test (duts). the duts shown here are orca series fpgas with dedicated boundary-scan circuitry. the test host is normally one of the following: automatic test equipment (ate), a workstation, a pc, or a micropro- cessor. 5-5972(f) key: bsc = boundary-scan cell, bdc = bidirectional data cell, and dcc = data control cell. figure 36. printed-circuit board with boundary- scan circuitry tdi tms tck tdo tdi tdo tms tck u2 net a net b net c plc array bdc bsc p_in p_ts scan out scan in pr[ij] dcc p_out bdc bsc p_in p_out p_ts pl[ij] dcc scan in scan out bdc dcc bsc p_in p_out p_ts scan out pb[ij] scan in tdo tck tms tdi tapc bypass register instruction register bdc dcc bsc p_in p_out p_ts scan out scan in pt[ij] see enlarged view below s tdi tdo tms tck u3 tdi tdo tms tck u4 tdi tdo tms tck u2
58 lucent technologies inc. data sheet june 1999 orca series 3c and 3t fpgas special function blocks (continued) 5-6765(f) figure 37. boundary-scan interface d[7:0] intr micro- processor d[7:0] ce ra r/w dav int sp tms0 tck tdi tdo tdi tms tck tdo orca series fpga tdi orca series fpga tms tck tdo tdi tms tck tdo orca series fpga lucent boundary- scan master (bsm) (dut) (dut) (dut) the boundary-scan support circuit shown in figure 37 is the 497aa boundary-scan master (bsm). the bsm off-loads tasks from the test host to increase test throughput. to interface between the test host and the duts, the bsm has a general microprocessor interface and provides parallel-to-serial/serial-to-parallel conver- sion, as well as three 8k data buffers. the bsm also increases test throughput with a dedicated automatic test-pattern generator and with compression of the test response with a signature analysis register. the pc- based boundary-scan test card/software allows a user to quickly prototype a boundary-scan test setup. boundary-scan instructions the orca series boundary-scan circuitry is used for three mandatory ieee 1149.1/d1 tests (extest, sample/preload, bypass), the optional ieee 1149.1/d1 idcode instruction, and five orca -defined instructions. the 3-bit wide instruction register sup- ports the nine instructions listed in table 13, where the use of psr1 or usercode is selectable by a bit stream option. table 13. boundary-scan instructions code instruction 000 extest 001 plc scan rin g 1 ( psr1 ) /usercode 010 ram write ( ram_w ) 011 idcode 100 sample/preload 101 plc scan rin g 2 ( psr2 ) 110 ram read ( ram_r ) 111 bypass
lucent technologies inc. 59 data sheet june 1999 orca series 3c and 3t fpgas special function blocks (continued) the external test (extest) instruction allows the inter- connections between ics in a system to be tested for opens and stuck-at faults. if an extest instruction is performed for the system shown in figure 36, the con- nections between u1 and u2 (shown by nets a, b, and c) can be tested by driving a value onto the given nets from one device and then determining whether the same value is seen at the other device. this is deter- mined by shifting 2 bits of data for each pin (one for the output value and one for the 3-state value) through the bsr until each one aligns to the appropriate pin. then, based upon the value of the 3-state signal, either the i/o pad is driven to the value given in the bsr, or the bsr is updated with the input value from the i/o pad, which allows it to be shifted out tdo. the sample/preload instruction is useful for sys- tem debugging and fault diagnosis by allowing the data at the fpgas i/os to be observed during normal operation or written during test operation. the data for all of the i/os is captured simultaneously into the bsr, allowing them to be shifted-out tdo to the test host. since each i/o buffer in the pics is bidirectional, two pieces of data are captured for each i/o pad: the value at the i/o pad and the value of the 3-state control sig- nal. for preload operation, data is written from the bsr to all of the i/os simultaneously. there are five orca -defined instructions. the plc scan rings 1 and 2 (psr1, psr2) allow user-defined internal scan paths using the plc latches/ffs. the ram_write enable (ram_w) instruction allows the user to serially configure the fpga through tdi. the ram_read enable (ram_r) allows the user to read back ram contents on tdo after configuration. the idcode instruction allows the user to capture a 32-bit identification code that is unique to each device and serially output it at tdo. the idcode format is shown in table 14. table 14. boundar y -scan id code * plc array size of fpga, reverse bit order. note: table assumes version 0. device version ( 4 bits ) part * ( 10 bits ) famil y ( 6 bits ) manufacturer ( 11 bits ) lsb ( 1 bit ) or3t20 0000 0011000000 110000 00000011101 1 or3t30 0000 0111000000 110000 00000011101 1 or3c/t55 0000 0100100000 110000 00000011101 1 or3c/t80 0000 0110100000 110000 00000011101 1 or3t125 0000 0011100000 110000 00000011101 1 or3t165 0000 0000010000 110000 00000011101 1
60 60 lucent technologies inc. data sheet june 1999 orca series 3c and 3t fpgas special function blocks (continued) orca boundary-scan circuitry the orca series boundary-scan circuitry includes a test access port controller (tapc), instruction register (ir), boundary-scan register (bsr), and bypass regis- ter. it also includes circuitry to support the four pre- defined instructions. figure 38 shows a functional diagram of the boundary- scan circuitry that is implemented in the orca series. the input pins (tms, tck, and tdi) locations vary depending on the part, and the output pin is the dedi- cated tdo/rd_data output pad. test data in (tdi) is the serial input data. test mode select (tms) controls the boundary-scan test access port controller (tapc). test clock (tck) is the test clock on the board. the bsr is a series connection of boundary-scan cells (bscs) around the periphery of the ic. each i/o pad on the fpga, except for cclk, done, and the boundary- scan pins (tck, tdi, tms, and tdo), is included in the bsr. the first bsc in the bsr (connected to tdi) is located in the first pic i/o pad on the left of the top side of the fpga (pta pic). the bsr proceeds clock- wise around the top, right, bottom, and left sides of the array. the last bsc in the bsr (connected to tdo) is located on the top of the left side of the array (pl1d). the bypass instruction uses a single ff, which resyn- chronizes test data that is not part of the current scan operation. in a bypass instruction, test data received on tdi is shifted out of the bypass register to tdo. since the bsr (which requires a two ff delay for each pad) is bypassed, test throughput is increased when devices that are not part of a test operation are bypassed. the boundary-scan logic is enabled before and during configuration. after configuration, a configuration option determines whether or not boundary-scan logic is used. the 32-bit boundary-scan identification register con- tains the manufacturers id number, unique part num- ber, and version (as described earlier). the identification register is the default source for data on tdo after reset if the tap controller selects the shift- data-register (shift-dr) instruction. if boundary scan is not used, tms, tdi, and tck become user i/os, and tdo is 3-stated or used in the readback operation. an optional usercode is available if the boundary- scan psr1 instruction is not used. the selection between psr1 and usercode is a configuration option and can be performed in orca foundry. the usercode is an 11-bit value that the user can set during device configuration and can be written to and read from the fpga via the boundary-scan logic. the usercode value replaces the manufacturer field of the boundary-scan id code when the usercode instruction is issued, allowing users to have configured devices identified in a user-defined manner. the manu- facturer id field remains available when the idcode instruction is issued. 5-5768(f) figure 38. orca series boundary-scan circuitry functional diagram tap controller tms tck boundary-scan register psr2 register (plcs) bypass register data mux instruction decoder instruction register m u x reset clock ir shift-ir update-ir pur tdo select enable reset clock dr shift-dr update-dr tdi data registers psr1 register (plcs) configuration register (ram_r, ram_w) prgm i/o buffers v dd v dd v dd v dd idcode register
lucent technologies inc. 61 data sheet june 1999 orca series 3c and 3t fpgas special function blocks (continued) orca series tap controller (tapc) the orca series tap controller (tapc) is a 1149.1/ d1 compatible test access port controller. the 16 jtag state assignments from the ieee 1149.1/d1 specifica- tion are used. the tapc is controlled by tck and tms. the tapc states are used for loading the ir to allow three basic functions in testing: providing test stimuli (update-dr), test execution (run-test/idle), and obtaining test responses (capture-dr). the tapc allows the test host to shift in and out both instructions and test data/results. the inputs and outputs of the tapc are provided in the table below. the outputs are primarily the control signals to the instruction register and the data register. table 15. tap controller in p ut/out p uts the tapc generates control signals that allow capture, shift, and update operations on the instruction and data registers. in the capture operation, data is loaded into the register. in the shift operation, the captured data is shifted out while new data is shifted in. in the update operation, either the instruction register is loaded for instruction decode, or the boundary-scan register is updated for control of outputs. the test host generates a test by providing input into the orca series tms input synchronous with tck. this sequences the tapc through states in order to perform the desired function on the instruction register or a data register. figure 39 provides a diagram of the state transitions for the tapc. the next state is deter- mined by the tms input value. 5-5370(f) figure 39. tap controller state transition diagram s y mbol i/o function tms i test mode select tck i test clock pur i powerup reset prgm i bscan reset treset o test lo g ic reset select o select ir ( hi g h ) ; select-dr ( low ) enable o test data out enable capture-dr o capture/parallel load-dr capture-ir o capture/parallel load-ir shift-dr o shift data re g ister shift-ir o shift instruction re g ister update-dr o update/parallel load-dr update-ir o update/parallel load-ir select- dr-scan capture-dr shift-dr exit1-dr pause-dr exit2-dr update-dr 1 1 0 0 10 run-test/ idle 1 test-logic- reset select- ir-scan capture-ir shift-ir exit1-ir pause-ir exit2-ir update-ir 1 1 0 10 00 0 0 1 0 1 1 1 0 1 1 0 0 0 0 1 11 0
62 62 lucent technologies inc. data sheet june 1999 orca series 3c and 3t fpgas special function blocks (continued) boundary-scan cells figure 40 is a diagram of the boundary-scan cell (bsc) in the orca series pics. there are four bscs in each pic: one for each pad, except as noted above. the bscs are connected serially to form the bsr. the bsc controls the functionality of the in, out, and 3-state signals for each pad. the bsc allows the i/o to function in either the normal or test mode. normal mode is defined as when an out- put buffer receives input from the plc array and pro- vides output at the pad or when an input buffer provides input from the pad to the plc array. in the test mode, the bsc executes a boundary-scan operation, such as shifting in scan data from an upstream bsc in the bsr, providing test stimuli to the pad, capturing test data at the pad, etc. the primary functions of the bsc are shifting scan data serially in the bsr and observing input (p_in), output (p_out), and 3-state (p_ts) signals at the pads. the bsc consists of two circuits: the bidirectional data cell is used to access the input and output data, and the direction control cell is used to access the 3-state value. both cells consist of a flip-flop used to shift scan data which feeds a flip-flop to control the i/o buffer. the bidirectional data cell is connected serially to the direc- tion control cell to form a boundary-scan shift register. the tapc signals (capture, update, shiftn, treset, and tck) and the mode signal control the operation of the bsc. the bidirectional data cell is also controlled by the high out/low in (holi) signal generated by the direction control cell. when holi is low, the bidirec- tional data cell receives input buffer data into the bsc. when holi is high, the bsc is loaded with functional data from the plc. the mode signal is generated from the decode of the instruction register. when the mode signal is high (extest), the scan data is propagated to the output buffer. when the mode signal is low (bypass or sample), functional data from the fpgas internal logic is propagated to the output buffer. the boundary-scan description language (bsdl) is provided for each device in the orca series of fpgas on the orca foundry cd. the bsdl is generated from a device profile, pinout, and other boundary-scan information. 5-2844(f figure 40. boundary-scan cell d q d q d q d q scan in p_out holi bidirectional data cell i/o buffer direction control cell mode update/tck scan out tck shiftn/capture p_ts p_in pad_in pad_ts pad_out 0 1 0 1 0 1 0 1 0 1
lucent technologies inc. 63 data sheet june 1999 orca series 3c and 3t fpgas special function blocks (continued) boundary-scan timing to ensure race-free operation, data changes on specific clock edges. the tms and tdi inputs are clocked in on the rising edge of tck, while changes on tdo occur on the falling edge of tck. in the execution of an extest instruction, parallel data is output from the bsr to the fpga pads on the falling edge of tck. the maximum fre- quency allowed for tck is 10 mhz. figure 41 shows timing waveforms for an instruction scan operation. the diagram shows the use of tms to sequence the tapc through states. the test host (or bsm) changes data on the falling edge of tck, and it is clocked into the dut on the rising edge. 5-5971(f) figure 41. instruction register scan timing diagram tck tms tdi run-test/idle run-test/idle exit1-ir exit2-ir update-ir select-dr-scan capture-ir select-ir-scan test-logic-reset shift-ir pause-ir shift-ir exit1-ir
64 64 lucent technologies inc. data sheet june 1999 orca series 3c and 3t fpgas microprocessor interface (mpi) the series 3 fpgas have a dedicated synchronous microprocessor interface function block (see figure 42). the mpi is programmable to operate with powerpc mpc800 series microprocessors and intel * i960 * j core processors; see table 16 and table 17, respectively, for compatible processors. the mpi imple- ments an 8-bit interface to the host processor ( pow- erpc or i960 ) that can be used for configuration and readback of the fpga as well as for user-defined data processing and general monitoring of fpga function. in addition to dedicated-function registers, the micro- processor interface allows for the control of up to 16 user registers (ram or flip-flops) in the fpga logic. a synchronous/asynchronous handshake procedure is used to control transactions with user logic in the fpga array. there is also capability for the fpga logic to interrupt the host processor either by a hard interrupt or by having the host processor poll the microprocessor interface. the control portion of the microprocessor interface is available following powerup of the fpga if the mode pins specify mpi mode, even if the fpga is not yet con- figured. the mode pin (m[2:0]) settings can be found in the fpga configuration modes section of this data sheet, and the setup and use of the mpi for configura- tion is discussed in the mpi setup and control subsec- tion. for postconfiguration use, the mpi must be included in the configuration bit stream by using an mpi library element in your design from the orca macro library, or by setting the mp_user bit of the mpi con- figuration control register prior to the start of configura- tion ( mpi registers are discussed later). * intel and i960 are registered trademarks of intel corporation. 5-5806(f) figure 42. mpi block diagram done rd_data init d7 d7in d7out d6 d6in d6out d5 d5in d5out d4 d4in d4out d3 d3in d3out d2 d2in d2out d1 d1in d1out d0 d0in d0out orca 3c/txxx mpi status register scratchpad register readback data register readback addr register control registers part id registers reset rd_cfg prgm gsr irq to gsr block to fpga routing user_start user_end wr_ctrl a[3:0] rdyrcv clk ads ale w/r i960 logic rd/wr bt ts clkout ta powerpc logic decode/control powerpc only a4 a3 a2 a1 a0 rd cs0 cs1 cclk m3 m2 m1 m0 mpi_irq mpi_ack mpi_clk mpi_strb mpi_ale mpi_rw mpi_b1 to fpga routing d[7:0]in d[7:0]out device pad i/o buffer
lucent technologies inc. 65 data sheet june 1999 orca series 3c and 3t fpgas microprocessor interface (mpi) (continued) powerpc system in figure 43, the orca fpga is a memory-mapped peripheral to the powerpc processor. the powerpc interface uses separate address and data buses and has several control lines. the orca chip select lines, cs0 and cs1, are each connected to an address line coming from the powerpc . in this manner, the fpga is capable of a transaction with the powerpc whenever the address line connected to cs0 is low, the address line for cs1 is high, and there is a valid address on powerpc address lines a[27:31]. other forms of selec- tion are possible by using the fpga chip selects in a different way. for example, powerpc address bits a[0:26] could be decoded to select cs0 and cs1, or if the fpga is the only peripheral to the powerpc , cs0 and cs1 could be tied low and high, respectively, to cause them to always be selected. if the mpi is not used for fpga configuration, decoding logic can be implemented internal or external to the fpga. if logic internal to the fpga is used, the chip selects must be routed out on an output pin and then connected exter- nally to cs0 and/or cs1. if the mpi is to be used for configuration, any decode logic used must be imple- mented external to the fpga since the fpga logic has not been configured yet. 5-5761(f) note: fpga shown as a memor y -mapped peripheral usin g cs0 and cs1. other decodin g schemes are possible usin g cs0 and/or cs1. figure 43. powerpc /mpi the basic flow of a transaction on the powerpc / mpi interface is given below. pin descriptions are shown in table 16 and timing is shown in the timing characteris- tics section of this data sheet. for both read and write transactions, the address, chip select, and read/write (read high, write low) signals are set up at the fpga pins by the powerpc . the powerpc then asserts its transfer start signal ( ts ) low. data is available to the mpi during a write at the rising clock edge after the clock cycle during which ts is low. the transfer is acknowledged to the powerpc by the low asser tion of the ta signal. the mpi powerpc interface does not support burst transfers, so the burst inhibit signal, bi , is also asserted low during the transfer acknowledge . the same process applies to a read from the mpi except that the read data is expected at the fpga data pins by the powerpc at the rising edge of the clock when ta is low. the mpi only drives ta low for one clock cycle. interrupt requests can be sent to the powerpc asyn- chronously to the read/write process. interrupt requests are sourced by the user-logic in the fpga. the mpi will assert the request to the powerpc as a direct interrupt signal and/or a pollable bit in the mpi status register (discussed in the mpi setup and control section). the mpi will continue to assert the interrupt request until the user-logic deasserts its interrupt request signal. table 16 . powerpc /mpi configuration dout cclk d[7:0] a[4:0] mpi_clk mpi_rw mpi_ack mpi_bi mpi_irq mpi_strb cs0 cs1 hdc ldc d[7:0] a[27:31] clkout rd/wr ta bi irq x ts a26 a25 to daisy- chained devices powerpc orca 8 fpga series 3 done init powerpc signal orca pin name mpi i/o function d [ 0:7 ] d [ 7:0 ] i/o 8-bit data bus a [ 27:31 ] a [ 4:0 ] i 5-bit mpi address bus ts rd/mpi_strb i transfer start si g nal cs0 i active-low mpi select cs1 i active-hi g h mpi select clkout a7/mpi_clk i powerpc interface clock rd/ wr a8/mpi_rw i read ( hi g h ) /write ( low ) si g nal ta a9/ mpi_ack o active-low transfer acknowled g e si g nal bi a10/ mpi_bi o active-low burst transfer inhibit si g nal an y of irq [ 7:0 ] a11/ mpi_irq o active-low interrupt re q uest si g nal
66 66 lucent technologies inc. data sheet june 1999 orca series 3c and 3t fpgas microprocessor interface (mpi) (continued) i960 system figure 44 shows a schematic for connecting the orca mpi to supported i960 processors. in the figure, the fpga is shown as the only peripheral, with the fpga chip select lines, cs0 and cs1, tied low and high, respectively. the i960 address and data are multi- plexed onto the same bus. this precludes memory mapping of the fpga in the i960 memory space of a multiperipheral system without some form of address latching to capture and hold the address signals to drive the cs0 and/or cs1 signals. multiple address sig- nals could also be decoded and latched to drive the cs0 and/or cs1 signals. if the mpi is not used for fpga configuration, decoding/latching logic can be implemented internal or external to the fpga. if logic internal to the fpga is used, the chip selects must be routed out an output pin and then connected externally to cs0 and/or cs1. if the mpi is to be used for configu- ration, any decode/latch logic used must be imple- mented external to the fpga since the fpga logic has not been configured yet. 5-5762 ( f ) note: fpga shown as onl y s y stem peripheral with fixed-chip select si g nals. for multiperipheral s y stems, address decodin g and/ or latchin g can be used to implement chip selects. figure 44. i960 /mpi the basic flow of a transaction on the i960 / mpi inter- face is given below. pin descriptions are shown in table 17, and timing is shown in the orca timing characteristics section of this data sheet. for both read and write transactions, the address latch enable (ale) is set up by the i960 at the fpga to the falling edge of the clock. the address, byte enables, chip selects, and read/write (read low, write high) signals are normally set up at the fpga pins by the i960 at the next rising edge of the clock. at this same rising clock edge, the i960 asserts its address/data strobe ( ads ) low. data is available to the mpi during a write at the rising clock edge of the following clock cycle. the transfer is acknowledged to the i960 by the low assertion of the ready/recover ( rdyrcv ) signal. the same process applies to a read from the mpi except that the read data is expected at the fpga data pins by the i960 at the rising edge of the clock when rdyrcv is low. the mpi only drives rdyrcv low for one clock cycle. interrupts can be sent to the i960 asynchronously to the read/write process. interrupt requests are sourced by the user-logic in the fpga. the mpi will assert the request to the i960 as a direct interrupt signal and/or a pollable bit in the mpi status register (discussed in the mpi setup and control section). the mpi will continue to assert the interrupt request until the user-logic deas- serts its interrupt request signal. table 17. i960 /mpi confi g uration dout cclk d[7:0] mpi_clk mpi_rw mpi_ack mpi_irq mpi_ale mpi_be1 hdc ldc to daisy- chained devices orca 8 fpga series 3 done init ad[7:0] clkin w/r rdyrcv xint x ale be1 i960 cs1 cs0 i960 system clock v dd mpi_be0 be0 mpi_strb ads i960 si g nal orca pin name mpi i/o function ad [ 7:0 ] d [ 7:0 ] i/o multiplexed 5-bit address/ 8-bit data bus. the address appears on d [ 4:0 ] . ale rdy/rclk/ mpi_ale i address latch enable used to capture address from ad [ 4:0 ] on fallin g ed g e of clock. ads rd / mpi_strb i address/data strobe to indicate start of transac- tion. cs0 i active-low mpi select. cs1 i active-hi g h mpi select. s y stem clock a7/ mpi_clk i i960 s y stem clock. this clock is sourced b y the s y stem and not the i960 . w/ r a8/mpi_rw i write ( hi g h ) /read ( low ) si g nal. rdyrcv a9/ mpi_ack o active-low read y /recover si g nal indicatin g acknowl- ed g ment of the transac- tion. an y of xint [ 7:0 ] a11/ mpi_irq o active-low interrupt re q uest si g nal. be0 a0/ mpi_be0 ib y te-enable 0 used as address bit 0 in i960 8-bit mode. be1 a1/ mpi_be1 ib y te-enable 1 used as address bit 1 in i960 8-bit mode.
lucent technologies inc. 67 data sheet june 1999 orca series 3c and 3t fpgas microprocessor interface (mpi) (continued) mpi interface to fpga the mpi interfaces to the user-programmable fpga logic using a 4-bit address, read/write control signal, interrupt request signal, and user start and user end handshake signals. timing numbers are provided so that the user-logic data transfers can be performed syn- chronously with the host processor ( powerpc or i960 ) interface clock or asynchronously. table 18 shows the internal interface signals between the mpi and the fpga user-programmable logic. all of the signals are connected to the mpi in the upper-left corner of the device except for the d[7:0] and clk signals that come directly from the i/o pin. the 4-bit addressing from the mpi to the plcs allows for up to 16 locations to be addressed by the host pro- cessor. the user address space of the mpi does not address any hard register. rather, the user is free to construct registers from ffs, latches, or ram that can be selected by the addressing. alternately, the decoded address signals may be used as control signals for other functions such as state machines or timers. the transaction sequence between the mpi and the user-logic is as follows. when the host processor ini- tiates a transaction as discussed in the preceding sec- tions, the mpi outputs the 4-bit user address (ua[3:0]) and the read/write control signal ( urdwr , which is read-high, write-low regardless of host processor), and then asserts the user start signal, ustart. during a write from the host processor, the user logic can accept data written by the host processor from the d[7:0] pins once the ustart signal is asserted. the user logic ends a transaction by asserting an active-high user end (uend) signal to the mpi . the mpi will insert wait-states in the host processor bus cycles, holding the host processor until the user- logic completes its task and returns a uend signal, upon which the mpi generates an acknowledge signal. if the host processor is reading from the fpga, the user logic must have the read data available on the d[7:0] pins of the fpga when the uend signal is asserted. if the user logic is fast or if the mpi user address is being decoded for use as a control signal, the mpi transaction time can be minimized by routing the ustart signal directly to the uend input of the mpi . the timing section of this data sheet contains a parameter table with delay, setup, and hold timing requirements to operate the user-logic either synchro- nously or asynchronously with the mpi host interface clock. the user-logic may also assert an active-low interrupt request ( uirq ) to the mpi , which, in turn, asserts an interrupt to the host processor. assertion of an inter- rupt request is asynchronous to the host processor clock and any read or write transaction occurring in the mpi . the user-logic is responsible for providing any required interrupt vectors for the host processor, and the user-logic must deassert the interrupt request once serviced. if the interrupt request is not deasserted in the user logic, it will continue to be asserted to the host processor via the mpi_irq pin. table 18. mpi internal interface si g nals si g nal mpi i/o function ua [ 3:0 ] o user lo g ic address . addresses up to 16 uni q ue user re g isters or use as control si g nals. urdwrn o user lo g ic read/write control si g nal . hi g h indicates a read from user lo g ic b y the host processor, low indicates a write to user-lo g ic b y the host processor. ustart o active-hi g h user start si g nal . indicates the start of an mpi transaction between the host processor and the user lo g ic. uend i active-hi g h user end si g nal . indicates that the user-lo g ic is finished with the current mpi transaction. uirq i active-low interru p t. sends re q uest from the user-lo g ic to the host processor. d [ 7:0 ] fpga i/o user data. ei g ht data bits come directl y from the fpga pinsnot throu g h the mpi . mpi_clk fpga i mpi clock. the mpi clock is sourced b y the host processor and comes directl y from the fpga pinnot throu g h the mpi .
68 lucent technologies inc. data sheet june 1999 orca series 3c and 3t fpgas microprocessor interface (mpi) (continued) mpi setup and control the mpi has a series of addressable registers that provide mpi control and status, configuration and readback data transfer, fpga device identification, and a dedicated user scratchpad register. all registers are 8 bits wide. the address map for these registers and the user-logic address space are shown in table 19, followed by descriptions of the register and bit functions. note that for all registers, the most significant bit is bit 7, and the least significant bi t is bit 0. table 19. mpi setu p and control re g isters control register 1 the mpi control register 1 is a read/write register. the host processor writes a control byte to configure the mpi . it is readable by the host processor to verify the status of control bits previously written. table 20. mpi setu p and control re g isters descri p tions address ( hex ) re g ister 00 control re g ister 1. 01 control re g ister 2. 02 scratchpad re g ister. 03 status re g ister. 04 confi g uration/readback data re g ister. 05 readback address re g ister 1 ( bits [ 7:0 ]) . 06 readback address re g ister 2 ( bits [ 15:8 ]) . 07 device id re g ister 1 ( bits [ 7:0 ]) . 08 device id re g ister 2 ( bits [ 15:8 ]) . 09 device id re g ister 3 ( bits [ 23:16 ]) . 0a device id re g ister 4 ( bits [ 31:24 ]) . 0b0f reserved. 101f user-definable address space. bit # descri p tion bit 0 gsr in p ut. settin g this bit to a 1 invokes a g lobal set/reset on the fpga. the host processor must return this bit to a 0 to remove the gsr si g nal. gsr does not affect the re g isters at mpi addresses 0 throu g h f hexadecimal or an y confi g uration re g isters. default state = 0. bit 1 reserved. bit 2 reserved. bit 3 reserved. bit 4 reserved. bit 5 rd_cfg in p ut. chan g in g this bit to a 0 after confi g uration will initiate readback. the host processor must return this bit to a 1 to remove the rd_cfg si g nal. since this bit works exactl y like the rd_cfg input pin, please see the fpga pin descriptions for more information on this si g nal. default state = 1. bit 6 reserved. bit 7 prgm in p ut. settin g this bit to a 0 causes the fpga to be g in confi g uration and resets the boundar y - scan circuitr y . the host processor must return this bit to a 1 to remove the prgm si g nal. since this bit works exactl y like the prgm input pin ( except that it does not reset the mpi ) , please see the fpga pin descriptions for more information on this si g nal. default state = 1.
lucent technologies inc. 69 data sheet june 1999 orca series 3c and 3t fpgas microprocessor interface (mpi) (continued) scratchpad register the mpi scratchpad register is an 8-bit read/write register with no defined operation. it may be used for any user- defined function. control register 2 the mpi control register 2 is a read/write register. the host processor writes a control byte to configure the mpi . it is readable by the host processor to verify the status of control bits it had previously written. table 21 . mpi control re g ister 2 bit # bit name descri p tion bit 0 en_irq_cfg enable irq for confi g uration data re q uest in dais y -chain confi g uration mode . settin g this bit to a 1 prior to confi g uration enables the irq si g nal to g o active when new data is re q uested for confi g uration writes or is available for confi g uration reads to/from the confi g uration data re g ister. a 0 clears the irq enable. this bit is onl y valid for dais y -chain confi g uration. default = 0. bit 1 en_irq_err enable irq for bit stream error . settin g this bit to a 1 prior to confi g uration enables the irq si g nal to g o active on the occurrence of a bit stream error durin g confi g uration. a 0 clears the irq enable. this bit onl y has effect while in confi g ura- tion mode. default = 0. bit 2 en_irq_usr enable irq from the user fpga s p ace . settin g this bit to a 1 allows user-defined circuitr y in the fpga to g enerate an interrupt to the host processor b y sourcin g a lo g ic low on the uirq si g nal in the user lo g ic. default = 0. bit 3 mp_daisy mpi dais y -chain out p ut enable . settin g this bit to a 1 enables dais y -chain output of the confi g uration data. see the confi g uration section of this data sheet for dais y - chain confi g uration details. default = 0. bit 4 mp_hold_bus enable bus holdin g durin g dais y -chain confi g uration mode . settin g this bit to a 1 will cause the mpi to wait until the fpga confi g uration lo g ic has serialized a b y te of confi g uration data before acknowled g in g the transaction. the data is onl y serialized if the mp_daisy ( bit 3 above ) control bit is set to 1. if mp_hold_bus is set to 0, the mpi will immediatel y acknowled g e a confi g uration data b y te transfer. immediate acknowled g ment allows the host processor to perform other tasks durin g fpga confi g uration b y pollin g the mpi status re g ister ( or b y interrupt ) and onl y write confi g uration data when the fpga is read y . default = 0. bit 5 mp_user mpi user mode enable . settin g this bit to a 1 will enable the mpi for user mode operation. mp_user must be set prior to the fpga done si g nal g oin g hi g h durin g confi g uration. the mpi ma y also be enabled for user operation via the confi g uration bit stream. default = 0. bit 6 reserved bit 7 reserved
70 lucent technologies inc. data sheet june 1999 orca series 3c and 3t fpgas microprocessor interface (mpi) (continued) status register the microprocessor interface status register is a read-only register, providing information to the host processor. table 22 . status re g ister configuration data register the mpi configuration data register is a writable register in configuration mode and a readable register in readback mode. for fpga configuration, this is where the configuration data bytes are sequentially written by the host pro- cessor. similarly, for readback mode, the mpi provides the readback data bytes in this register for the host proces- sor. readback address register 1 the mpi readback address register 1 is a writable register used to accept the least significant address byte (bits [7:0]) of the configuration data location to be read back. readback address register 2 the mpi readback address register 2 is a writable register used to accept the most significant address byte (bits [15:8]) of the configuration data location to be read back. bit # descri p tion bit 0 reserved . bit 1 data read y . set b y the mpi , a 1 on this bit durin g confi g uration alerts the host processor that the fpga is read y for another b y te of confi g uration data. durin g b y te-wide readback, the mpi sets this bit to a 1 to tell the host processor that a b y te of confi g uration data is available for readin g . this bit is cleared b y a host processor access ( read or write ) to the confi g uration data re g ister. bit 2 irq pendin g . the mpi sets this bit to 1 to indicate to the host processor that the fpga has a pendin g interrupt re q uest. this bit ma y be used for the host processor to poll for interrupts if the mpi_irq pin out- put of the fpga has been masked at the host processor. this bit is set to 0 when the status re g ister is read. interrupt re q uests from the fpga user space must be cleared in fpga user lo g ic in addition to readin g this bit. bits [ 4:3 ] bit stream error fla g s . bits 3 and 4 are set b y the mpi to indicate an y error durin g fpga confi g ura- tion. see bit 2 of control re g ister 2 for the capabilit y to alert the host processor of an error via the irq si g nal durin g confi g uration. in the truth table below, bit 3 is the lsb ( bit on ri g ht ) . these bits are cleared to 0 when prgm g oes active: 00 = no error 01 = id error 10 = checksum error 11 = stop-bit/ali g nment error bit 5 reserved . bit 6 init . this bit reflects the binar y value of the fpga init pin. bit 7 done . this bit reflects the binar y value of the fpga done pin.
lucent technologies inc. 71 data sheet june 1999 orca series 3c and 3t fpgas microprocessor interface (mpi) (continued) device id registers the mpi device id is broken into four registers holding 1 byte each. the device id that is available through the mpi is the same as the boundary-scan id code, except that the device id in the mpi has a reverse bit order. there is no means to overwrite any of the device id as can be done with the boundary-scan id, but the mpi scratchpad register can be used as a personalization register. the format for the entire device id is shown below followed by family and device values and the partitioning of the device id into the four device id registers. table 23 . device id code * plc arra y size of fpga. table 24 shows the family and device values for all parts covered by this data sheet. table 24 . series 3 famil y and device id values table 25 describes the device ids for all parts covered by this data sheet as they are partitioned into the four regis- ters found in the mpi . table 25 . orca series 3 device id descri p tions version part * famil y manufacturer msb 4 bits 10 bits 6 bits 11 bits 1 bit example: ( first version of lucents or3c55 ) 0000 0100100000 110000 00000011101 1 part name famil y id ( hex ) device id ( hex ) or3t20 03 0c or3t30 03 0e or3c/t55 03 12 or3c/t80 03 16 or3t125 03 1c device id re g ister 1 bit 0 lo g ic 1. this bit is alwa y s a one. bits [ 7:1 ] 0011101, the 7 least si g nificant bits of the lucent technolo g ies manufacturer id. device id re g ister 2 bits [ 3:0 ] 0000, the 4 most si g nificant bits of the lucent technolo g ies manufacturer id. bits [ 7:4 ] the 4 least si g nificant bits of the 10-bit part number. device id re g ister 3 bits [ 5:0 ] the 6 most si g nificant bits of the 10-bit part number. bits [ 7:6 ] the 2 least si g nificant bits of the device famil y code. device id re g ister 4 bits [ 3:0 ] the 4 most si g nificant bits of the device famil y code. bits [ 7:4 ] the 4-bit device version code.
72 72 lucent technologies inc. data sheet june 1999 orca series 3c and 3t fpgas programmable clock manager (pcm) the orca programmable clock manager ( pcm ) is a special function block that is used to modify or condi- tion clock signals for optimum system performance. some of the functions that can be performed with the pcm are clock skew reduction (both internal and board level), duty-cycle adjustment, clock delay reduction, clock phase adjustment, and clock frequency multipli- cation/division. due to the different capabilities required by customer application, each pcm contains both a pll (phase-locked loop) and a dll (delayed-locked loop) mode. by using plc logic resources in conjunc- tion with the pcm , many other functions, such as fre- quency synthesis, are possible. there are two pcms on each series 3 device, one in the lower left corner and one in the upper right corner. each can drive two different, but interrelated clock net- works inside the fpga. each pcm can take a clock input from the expressclk pad in its corner or from general routing resources. there are also two input sources that provide feedback to the pcm from the plc array. one of these is a dedicated corner express- clk feedback, and the other is from general routing. each pcm sources two clock outputs, one to the corner expressclk that feeds the clkcntrl blocks on the two sides adjacent to the pcm , and one to the system clock spine network through general routing. figure 45 shows a high-level block diagram of the pcm . functionality of the pcm is programmed during opera- tion through a read/write interface internal to the fpga array or via the configuration bit stream. the internal fpga interface comprises write enable and read enable signals, a 3-bit address bus, an 8-bit input (to the pcm ) data bus, and an 8-bit output data bus. there is also a pcm output signal, lock, that indicates a sta- ble output clock state. these signals are used to pro- gram a series of registers to configure the pcm functional core for the desired functionality. operation of the pcm is divided into two modes, delay- locked loop (dll) and phase-locked loop (pll). some operations can be performed by either mode and some are specific to a particular mode. these will be described in each individual mode section. in general, dll mode is preferable to pll mode for the same func- tion because it is less sensitive to input clock noise. in the discussions that follow, the duty cycle is the per- cent of the clock period during which the output clock is high. 5-5828(f) figure 45. pcm block diagram user control signals pcm-fpga interface pcm core functions corner expressclk in general clockin feedback expressclk feedback clock from routing expressclk out system clock out (from general routing) (to general routing)
lucent technologies inc. 73 data sheet june 1999 orca series 3c and 3t fpgas programmable clock manager (pcm) (continued) pcm registers the pcm contains eight user-programmable registers used for configuring the pcm s functionality. table 26 shows the mapping of the registers and their functions. see figure 46 for more information on the location of pcm ele- ments that are discussed in the table. the pcm registers are referenced in the discussions that follow. detailed explanations of all register bits are supplied following the functional description of the pcm . table 26 . pcm re g isters address function 0 divider 0 pro g rammin g . pro g rammable divider, div0, value and div0 reset bit. div0 can divide the input clock to the pcm or can be b y passed. 1 divider 1 pro g rammin g . pro g rammable divider, div1, value and div1 reset bit. div1 can divide the feedback clock input to the pcm or can be b y passed. valid onl y in pll mode. 2 divider 2 pro g rammin g . pro g rammable divider, div2, value and div2 reset bit. div2 can divide the output of the tapped dela y line or can be b y passed and is onl y valid for the expressclk output. 3 dll 2x dut y -c y cle pro g rammin g . dll mode clock doubler ( 2x ) dut y -c y cle selection. 4 dll 1x dut y -c y cle pro g rammin g . dependin g on the settin g s in other re g isters, this re g is- ter is for: a. pll mode phase/dela y selection; b. dll mode 1x dut y c y cle selection; and c. dll mode pro g rammable dela y . 5 mode pro g rammin g . dll/pll mode selection, dll 1x/2x clock selection, phase detector feedback selection. 6 clock source status/out p ut clock selection pro g rammin g . input clock selection, feed- back clock selection, expressclk output source selection, s y stem clock output source selec- tion. 7 pcm control pro g rammin g . pcm power, reset, and confi g uration control.
74 lucent technologies inc. data sheet june 1999 orca series 3c and 3t fpgas programmable clock manager (pcm) (continued) 5-5829(f) figure 46. pcm functional block diagram expressclk from programmable divider div0 register 7 register 6 register 5 register 4 register 3 register 2 register 1 register 0 fpga-pcm interface combinatorial logic programmable divider div2 0 1 2 3 s4 0 1 2 3 s10 0 system clock output expressclk output from expressclk feedback feedback clock programmable divider div1 0 1 s2 phase detector programmable delay lines (32 taps) charge pump and low-pass filter 1 0 s4 1...7 s5 1...7 1...7 1...7 s6 s7 s8 0 1 2 3 s4 0 1 2 3 s3 pcm input clock data_in[7:0] addr_in[2:0] data_out[7:0] we re lock pad routing 0 1 2 3 s0 routing
lucent technologies inc. 75 data sheet june 1999 orca series 3c and 3t fpgas programmable clock manager (pcm) (continued) delay-locked loop (dll) mode dll mode is used for implementing a delayed clock (phase adjustment), clock doubling, and duty cycle adjustment. all dll functions stem from a delay line with 32 taps. the delayed input clock is pulled from var- ious taps and processed to implement the desired result. there is no feedback clock in dll mode, provid- ing a very stable output and a fast lock time for the out- put clock. dll mode is selected by setting bit 0 in pcm register five to a 0. the settings for the various submodes of dll mode are described in the following paragraphs. divider div0 may be used with any of the dll modes to divide the input clock by an integer factor of 1 to 8 prior to implementation of the dll process. delayed clock a delayed version of the input clock can be constructed in dll mode. the output clock can be delayed by increments of 1/32 of the input clock period. express clk and system clk outputs in delay modes are selected by setting register six, bits [5:4] to 10 or 11 for expressclk output, and/or bits [7:6] to 10 for system clock output. the delay value is entered in register four. see register four programming details for more infor- mation. delay values are also shown in the second col- umn of table 27. note that when register six, bits [5:4] are set to 11, the expressclk output is divided by an integer factor from 1 to 8 while the system clock cannot be divided. the expressclk divider is provided so that the i/o clocking provided by the expressclk can operate slower than the internal system clock. this allows for very fast inter- nal processing while maintaining slower interface speeds off-chip for improved noise and power perfor- mance or to interoperate with slower devices in the sys- tem. the divisor of the expressclk frequency is selected in register two. see the register two program- ming details for more information. 1x clock duty-cycle adjustment a duty-cycle adjusted replica of the input clock can be constructed in dll mode. the duty cycle can be adjusted in 1/32 (3.125%) increments of the input clock period. dll 1x clock mode is selected by setting bit 4 of register five to a 1, and output clock source selection is selected by setting register six, bits [5:4] to 01 for expressclk output, and/or bits [7:6] to 01 for system clock output. the duty-cycle percentage value is entered in register four. see register four programming details for more information. duty cycle values are also shown in the third column of table 27. table 27. dll mode dela y /1x dut y c y cle pro g rammin g values re g ister 4 [7:0] 7 6 5 4 3 2 1 0 dela y ( clk_in/32 ) dut y c y cle ( % of clk_in ) 0 0 x x x 0 0 0 1 3.125 0 0 x x x 0 0 1 2 6.250 0 0 x x x 0 1 0 3 9.375 0 0 x x x 0 1 1 4 12.500 0 0 x x x 1 0 0 5 15.625 0 0 x x x 1 0 1 6 18.750 0 0 x x x 1 1 0 7 21.875 0 0 x x x 1 1 1 8 25.000 0 1 x x x 0 0 0 9 28.125 0 1 x x x 0 0 1 10 31.250 0 1 x x x 0 1 0 11 34.375 0 1 x x x 0 1 1 12 37.500 0 1 x x x 1 0 0 13 40.625 0 1 x x x 1 0 1 14 43.750 0 1 x x x 1 1 0 15 46.875 0 1 1 1 1 x x x 16 50.000 1 0 0 0 0 x x x 17 53.125 1 0 0 0 1 x x x 18 56.250 1 0 0 1 0 x x x 19 59.375 1 0 0 1 1 x x x 20 62.500 1 0 1 0 0 x x x 21 65.625 1 0 1 0 1 x x x 22 68.750 1 0 1 1 0 x x x 23 71.875 1 0 1 1 1 x x x 24 75.000 1 1 0 0 0 x x x 25 78.125 1 1 0 0 1 x x x 26 81.250 1 1 0 1 0 x x x 27 84.375 1 1 0 1 1 x x x 28 87.500 1 1 1 0 0 x x x 29 90.625 1 1 1 0 1 x x x 30 93.750 1 1 1 1 0 x x x 31 96.875
76 76 lucent technologies inc. data sheet june 1999 orca series 3c and 3t fpgas programmable clock manager (pcm) (continued) 2x clock duty-cycle adjustment a doubled-frequency, duty-cycle adjusted version of the input clock can be constructed in dll mode. the first clock cycle of the 2x clock output occurs when the input clock is high, and the second cycle occurs when the input clock is low. the duty cycle can be adjusted in 1/32 (6.25%) increments of the input clock period. additionally, each of the two doubled-clock cycles that occurs in a single input clock cycle may be adjusted to have different duty cycles. dll 2x clock mode is selected by setting bit 4 of register five to a 1, and by setting register six, bits [5:4] to 01 for expressclk out- put, and/or bits [7:6] to 01 for system clock output. the duty-cycle percentage value is entered in register three. see register three programming details for more information. duty-cycle values where both cycles of the doubled clock have the same duty cycle are also shown in table 28. table 28 . dll mode dela y /2x dut y c y cle pro g rammin g values phase-locked loop (pll) mode the pll mode of the pcm is used for clock multiplica- tion (1/8x to 64x) and clock delay minimization func- tions. pll functions make use of the pcm dividers and use feedback signals, often from the fpga array. the use of feedback is discussed with each pll submode. pll mode is selected by setting bit 0 of register five to 1. clock delay minimization pll mode can be used to minimize the effects of the input buffer and input routing delay on the clock signal. pll mode causes a feedback clock signal to align in phase with the input clock (refer back to the block dia- gram in figure 45) so that the delay between them is effectively eliminated. there is a dedicated feedback path from an adjacent middle clkcntrl block to the pcm . using the corner expressclk pad as the input to the pcm and using this dedicated feedback path, the clock from the express- clk output of the pcm , as viewed at the clkcntrl block, will be phase-aligned with the expressclk input to the pcm . these relationships are diagrammed in figure 47. a feedback clock can also be input to the pcm from general routing. this allows for compensating for delay between the pcm input and a point in the general rout- ing. the use of this routed-feedback path is not gener- ally recommended. because compensation is based on the programmable routing, the amount of clock delay compensation can vary between fpga lots and fabrication processes, and will vary each time that the feedback line is routed using different resources. con- tact lucent technologies for application notes regard- ing the use of routed-feedback delay compensation. 5-5980(f) fi g ure 47. ex p ressclk dela y minimization usin g the pcm re g ister 3 [7:0] 7 6 5 4 3 2 1 0 dut y c y cle ( % ) 0 0 0 0 0 0 0 0 6.25 0 0 0 0 1 0 0 1 12.50 0 0 0 1 0 0 1 0 18.75 0 0 0 1 1 0 1 1 25.00 0 0 1 0 0 1 0 0 31.25 0 0 1 0 1 1 0 1 37.50 0 0 1 1 0 1 1 0 43.75 0 0 1 1 1 1 1 1 50.00 1 1 0 0 0 0 0 0 56.25 1 1 0 0 1 0 0 1 62.50 1 1 0 1 0 0 1 0 68.75 1 1 0 1 1 0 1 1 75.00 1 1 1 0 0 1 0 0 81.25 1 1 1 0 1 1 0 1 87.50 1 1 1 1 0 1 1 0 93.75 corner clkcntrl clkcntrl delay delay is compensated input output without using pcm output expressclk expressclk using pcm expressclk compensation equals delay
lucent technologies inc. 77 data sheet june 1999 orca series 3c and 3t fpgas programmable clock manager (pcm) (continued) clock multiplication an output clock that is a multiple (not necessarily an integer multiple) of the input clock can be generated in pll mode. the multiplication ratio is programmed in the division registers div0, div1, and div2. note that div2 applies only to the expressclk output of the pcm and any reference to div2 is implicitly 1 for the system clock output of the pcm . the clock multiplica- tion formulas when using expressclk feedback are: where the values of div0, div1, and div2 range from 1 to 8. the expressclk multiplication range of output clock frequencies is, therefore, from 1/8x up to 8x, with the system clock range up to 8x the expressclk frequency or 64x the input clock frequency. if system clock feed- back is used, the formulas are: the divider values, div0, div1, and div2 are pro- grammed in registers zero, one, and two, respectively. the multiplied output is selected by setting register six, bits [5:4] to 10 or 11 for expressclk output and/or bits [7:6] to 10 for system clock output. note that when reg- ister six, bits [5:4] are set to 11, the expressclk output is divided by div2, while the system clock cannot be divided. the expressclk divider is provided so that the i/o clocking provided by the expressclk can operate slower than the internal system clock. this allows for very fast internal processing while maintaining slower interface speeds off-chip for improved noise and power performance or to interoperate with slower devices in the system. it is also necessary to configure the internal pcm oscil- lator for operation in the proper frequency range. table 29 and table 30 show the settings required for register four for a given frequency range for series 3c and 3t devices. in addition, the acquisition time is shown for each frequency range. this is the time that is required for the pcm to acquire lock. the pcm oscil- lator frequency range is chosen based on the desired output frequency at the system clock output. if using the expressclk output, the equivalent system clock frequency can be selected by multiplying the expected expressclk output frequency by the value for div2. choose the nominal frequency from the table that is closest to the desired frequency, and use that value to program register four. minor adjustments to match the exact input frequency are then performed automatically by the pcm . f expressclk_out = f input_clock ? div1 div0 f system_clock_out = f expressclk_out ? div2 f system_clock_out = f input_clock ? div1 div0 f expressclk_out = f system_clock / div2
78 78 lucent technologies inc. data sheet june 1999 orca series 3c and 3t fpgas programmable clock manager (pcm) (continued) table 29 . pcm oscillator fre q uenc y ran g e 3txxx note: use of settin g s in the first three rows is not recommended. x means dont care. table 30 . pcm oscillator fre q uenc y ran g e 3cxx note: use of settin g s in the first three rows is not recommended. x means dont care. re g ister 4 76543210 min ( mhz ) s y stem clock out p ut fre q uenc y ( mhz ) nom max ( mhz ) t ac q uisition ( s ) 00xxx010 17.00 58.50 100.00 36.00 00xxx011 16.10 52.50 89.00 37.00 00xxx100 15.17 49.00 82.80 38.00 00xxx101 14.25 45.00 76.50 39.00 00xxx110 13.33 41.50 70.30 40.00 00xxx111 12.40 38.00 64.00 41.00 01xxx000 12.20 36.75 61.30 43.75 01xxx001 12.10 35.00 58.00 46.50 01xxx010 11.90 33.00 54.30 49.25 01xxx011 11.70 31.30 51.00 52.00 01xxx100 11.10 30.00 49.40 54.75 01xxx101 10.50 29.15 47.80 57.50 01xxx110 10.00 28.10 46.20 60.25 01xxx111 9.40 27.00 44.60 63.00 10000xxx 9.20 26.25 43.30 65.40 10001xxx 9.00 25.65 42.30 67.80 10010xxx 8.80 25.00 41.30 70.10 10011xxx 8.60 24.45 40.30 72.50 10100xxx 8.40 23.70 39.00 74.90 10101xxx 8.10 22.90 37.70 77.30 10110xxx 7.90 22.20 36.50 79.60 10111xxx 7.70 21.50 35.20 82.00 11000xxx 7.60 20.80 34.00 84.30 11001xxx 7.45 20.10 32.80 86.50 11010xxx 7.30 19.45 31.60 88.80 11011xxx 7.20 18.85 30.50 91.00 11100xxx 6.60 18.30 30.00 93.30 11101xxx 6.00 17.70 29.40 95.50 11110xxx 5.50 17.10 28.60 97.80 11111xxx 5.00 16.50 28.00 100.00 re g ister 4 76543210 min ( mhz ) s y stem clock out p ut fre q uenc y ( mhz ) nom max ( mhz ) t ac q uisition ( s ) 00xxx010 10.50 73.00 135.00 36.00 00xxx011 10.00 68.00 126.00 37.00 00xxx100 9.50 63.00 117.00 38.00 00xxx101 9.10 58.50 108.00 39.00 00xxx110 8.60 53.80 99.00 40.00 00xxx111 8.10 49.00 90.00 41.00 01xxx000 7.80 47.70 87.50 43.80 01xxx001 7.60 46.30 85.00 46.50 01xxx010 7.30 45.00 82.50 49.30 01xxx011 7.10 43.60 80.00 52.00 01xxx100 6.80 42.10 77.50 55.00 01xxx101 6.50 40.75 75.00 57.50 01xxx110 6.30 39.40 72.50 60.30 01xxx111 6.00 38.00 70.00 63.00 10000xxx 5.90 37.40 68.80 65.40 10001xxx 5.90 36.70 67.50 67.80 10010xxx 5.80 36.00 66.30 70.10 10011xxx 5.80 35.40 65.00 72.50 10100xxx 5.70 35.00 63.80 74.90 10101xxx 5.60 34.10 62.50 77.30 10110xxx 5.60 33.50 61.30 79.60 10111xxx 5.50 32.80 60.00 82.00 11000xxx 5.40 32.10 58.80 84.30 11001xxx 5.40 31.50 57.50 86.50 11010xxx 5.30 30.70 56.30 88.80 11011xxx 5.30 30.10 55.00 91.00 11100xxx 5.20 29.50 53.80 93.30 11101xxx 5.10 28.80 52.50 95.50 11110xxx 5.10 28.20 51.30 97.80 11111xxx 5.00 27.50 50.00 100.00
lucent technologies inc. 79 data sheet june 1999 orca series 3c and 3t fpgas programmable clock manager (pcm) (continued) pcm/fpga internal interface writing and reading the pcm registers is done through a simple asynchronous interface that connects with the fpga routing resources. reads from the pcm by the fpga logic are accomplished by setting up the 3-bit address, a[2:0], and then applying an active-high read enable (re) pulse. the read data will be available as long as re is held high. the address may be changed while re is high, to read other addresses. when re goes low, the data output bus is 3-stated. writes to the pcm by the fpga logic are performed by applying the write data to the data input bus of the pcm , applying the 3-bit address to write to, and assert- ing the write enable (we) signal high. data will be writ- ten by the high-going transition of the we pulse. the read enable (re) and write enable (we) signals may not be active at the same time. for detailed timing information and specifications, see the timing charac- teristics section of this data sheet. the lock signal output from the pcm to the fpga routing indicates a stable output clock signal from the pcm . the lock signal is high when the pcm output clock parameters fall within the programmed values and the pcm specifications for jitter. due to phase cor- rections that occur internal to the pcm , the lock sig- nal might occasionally pulse low when the output clock is out of specification for only one or two clock cycles (high jitter due to temperature, voltage fluctuation, etc.) to accommodate these pulses, it is suggested that the user integrate the lock signal over a period suitable to their application to achieve the desired usage of the lock signal. the lock signal will also pulse high and low during the acquisition time as the output clock stabilizes. true lock is only achieved when the lock signal is a solid high. again, it is suggested that the user integrate the lock signal over a time period suitable to the subject application. pcm operation several features are available for the control of the pcm s overall operation. the pcm may be programma- bly enabled/disabled via bit 0 of register 7. when dis- abled, the analog power supply of the pcm is turned off, conserving power and eliminating the possibility of inducing noise into the system power buses. individual bits (register 7, bits [2:1]) are provided to reset the dll and pll functions of the pcm . these resets affect only the logic generating the dll or pll function; they do not reset the divider values (div0, div1, div2) or reg- isters [7:0]. the global set/reset (gsrn) is also pro- grammably controlled via register 7, bit 7. if register 7, bit 7 is set to 1, gsrn will have no effect on the pcm logic, allowing the clock to operate during a global set/reset. this function allows the fpga to be reset without affecting a clock that is sent off-chip and used elsewhere in the system. bit 6 of register 7 affects the functionality of the pcm during configuration. if set to 1, this bit enables the pcm to operate during configura- tion, after the pcm has been configured. the pcm functionality is programmed via the bit stream. if regis- ter 7, bit 6 is 0, the pcm cannot function and its power supply is disabled until after the configuration done signal goes high. when the pcm is powered up via register 7, bit 0, there is a wake-up time associated with its operation. follow- ing the wake-up time, the pcm will begin to fully func- tion, and, following an acquisition time during which the output clock may be unstable, the pcm will be in steady-state operation. there is also a shutdown time associated with powering off the pcm . the output clock will be unstable during this period. waveforms and timing parameters can be found in the timing characteristics section of this data sheet.
80 lucent technologies inc. data sheet june 1999 orca series 3c and 3t fpgas programmable clock manager (pcm) (continued) pcm detailed programming descriptions of bit fields and individual control bits in the pcm control registers are provided in table 31. refer to figure 46 for more information on the location of the pcm elements that are discussed. in the following discussion, the duty cycle is in the percentage of the clock period where the clock is high. table 31 . pcm control re g isters bit # function re g ister 0divider 0 pro g rammin g bits [ 3:0 ] 4-bit divider, div0, value . this value enables the input clock to immediatel y be divided b y a value from 1 to 8. a 0 value ( the default ) indicates that div0 is b y passed ( no division ) . b y pass incurs less dela y than dividin g b y 1. hexadecimal values g reater than 8 for bits [ 3:0 ] y ield their modulo 8 value. for example, if bits [ 3:0 ] are 1001 ( 9 hex ) , the result is divide b y 1 ( remainder 9/8 = 1 ) . bits [ 6:4 ] reserved . bit 7 div 0 reset bit . div0 ma y not be reset b y gsrn dependin g on the value of re g ister 7, bit 7. this bit ma y be set to 1 to reset div0 to its default value. bit 0 must be set to 0 ( the default ) to remove the reset. re g ister 1divider 1 pro g rammin g bits [ 3:0 ] 4-bit divider, div1, value . this value enables the feedback clock to be divided b y a value from 1 to 8. a 0 value ( the default ) indicates that div1 is b y passed ( no division ) . b y pass incurs less dela y than dividin g b y 1. hexadecimal values g reater than 8 for bits [ 3:0 ] y ield their modulo 8 value. for example, if bits [ 3:0 ] are 1001 ( 9 hex ) , the result is divide b y 1 ( remainder 9/8 = 1 ) . bits [ 6:4 ] reserved . bit 7 div1 reset bit . div1 ma y not be reset b y gsrn, dependin g on the value of re g ister 7, bit 7. this bit ma y be set to 1 to reset div1 to its default value. bit 0 must be set to 0 ( the default ) to remove the reset. re g ister 2divider 2 pro g rammin g bits [ 3:0 ] 4-bit divider, div2, value . this value enables the tapped dela y line output clock driven onto expressclk to be divided b y a value from 1 to 8. a 0 value ( the default ) indicates that div2 is b y passed ( no division ) . b y pass incurs less dela y than dividin g b y 1. hexadecimal values g reater than 8 for bits [ 3:0 ] y ield their modulo 8 value. for example, if bits [ 3:0 ] are 1001 ( 9 hex ) , the result is divide b y 1 ( remainder 9/8 = 1 ) . bits [ 6:4 ] reserved . bit 7 div2 reset bit . div2 ma y not be reset b y gsrn, dependin g on the value of re g ister 7, bit 7. this bit ma y be set to 1 to reset div2 to its default value. bit 7 must be set to 0 ( the default ) to remove the reset. re g ister 3dll 2x dut y -c y cle pro g rammin g bits [ 2:0 ] dut y -c y cle selection for the doubled clock period associated with the input clock hi g h. the dut y c y cle is ( value of bit 6 ) * 50% + (( value of bits [ 2:0 ]) + 1 ) * 6.25%. see the description for bit 6. bits [ 5:3 ] dut y -c y cle selection for the doubled clock period associated with the input clock low. the dut y c y cle is ( value of bit 7 ) * 50% + (( value of bits [ 2:0 ]) + 1 ) * 6.25%. see the description for bit 7. bit 6 master dut y -c y cle control for the first clock period of the doubled clock: 0 = less than or e q ual to 50%, 1 = g reater than 50%. bit 7 master dut y -c y cle control for the second clock period of the doubled clock: 0 = less than or e q ual to 50%, 1 = g reater than 50%. example: both clock periods havin g a 62.5% dut y c y cle, bits [ 7:0 ] are 11 001 001.
lucent technologies inc. 81 data sheet june 1999 orca series 3c and 3t fpgas programmable clock manager (pcm) (continued) table 31. pcm control registers (continued) bit # function re g ister 4dll 1x dut y -c y cle pro g rammin g bits [ 2:0 ] dut y -c y cle/dela y selection for dut y c y cle/dela y s less than or e q ual to 50% . the dut y - c y cle/dela y is ( value of bits [ 7:6 ]) * 25% + (( value of bits [ 2:0 ]) + 1 ) * 3.125%. see the description for bits [ 7:6 ] . bits [ 5:3 ] dut y -c y cle/dela y selection for dut y c y cle/dela y s greater than 50% . the dut y -c y cle/dela y is ( value of bits [ 7:6 ]) * 25% + (( value of bits [ 5:3 ]) + 1 ) * 3.125%. see the description for bits [ 7:6 ] . bits [ 7:6 ] master dut y c y cle control : 00: dut y c y cle 3.125% to 25% 01: dut y c y cle 28.125% to 50% 10: dut y c y cle 53.125% to 75% 11: dut y c y cle 78.125% to 96.875% example: a 40.625% dut y c y cle, bits [ 7:0 ] are 01 xxx 100, where x is a dont care because the dut y c y cle is not g reater than 50%. example: the pcm output clock should be dela y ed 96.875% ( 31/32 ) of the input clock period. bits [ 7:0 ] are 11110xxx, which is 78.125% from bits [ 7:6 ] and 18.75% from bits [ 5:3 ] . bits [ 2:0 ] are dont care ( x ) because the dela y is g reater than 50%. re g ister 5mode pro g rammin g bit 0 dll/pll mode selection bit . 0 = dll, 1 = pll. default is dll mode. bit 1 reserved . bit 2 pll phase detector feedback in p ut selection bit . 0 = feedback si g nal from routin g / expressclk , 1 = feedback from pro g rammable dela y line output. default is 0. has no effect in dll mode. bit 3 reserved . bit 4 1x/2x clock selection bit for dll mode . 0 = 1x clock output, 1 = 2x clock output. default is 1x clock output. has no effect in pll mode. bits [ 7:5 ] reserved .
82 lucent technologies inc. data sheet june 1999 orca series 3c and 3t fpgas programmable clock manager (pcm) (continued) table 31. pcm control registers (continued) bit # function bits [ 5:4 ] expressclk out p ut source selector . default is 00. 00: pcm input clock, b y pass path throu g h pcm 01: dll output 10: tapped dela y line output 11: divided ( div2 ) dela y line output bits [ 7:6 ] s y stem clock out p ut source selector . default is 00. 00: pcm input clock, b y pass path throu g h pcm 01: dll output 10: tapped dela y line output 11: reserved re g ister 7pcm control pro g rammin g bit 0 pcm analo g power su pp l y switch . 1 = power suppl y on, 0 = power suppl y off. bit 1 pcm reset . a value of 1 resets all pcm lo g ic for pll and dll modes. bit 2 dll reset . a value of 1 resets the clock g eneration lo g ic for dll mode. no dividers or user re g - isters are affected. bits [ 5:3 ] reserved . bit 6 pcm confi g uration o p eration enable bit . 0 = normal confi g uration operation. durin g confi g u- ration ( done = 0 ) , the pcm analo g power suppl y will be off, the pcm output data bus is 3-stated, and the lock si g nal is asserted to lo g ic 0. the pcm will power up when done = 1. 1 = pcm operation durin g confi g uration. the pcm ma y be powered up ( see bit 0 ) and be g in operation, or continue operation. the setup of the pcm can be performed via the confi g uration bit stream. bit 7 pcm gsrn enable bit . 0 = normal gsrn operation. 1 = gsrn has no effect on pcm lo g ic, so clock processin g will not be interrupted b y a chip reset. default is 0.
lucent technologies inc. 83 data sheet june 1999 orca series 3c and 3t fpgas programmable clock manager (pcm) (continued) pcm applications the applications discussed below are only a small sampling of the possible uses for the pcm . check the lucent technologies orca fpga internet website (listed at the end of this data sheet) for additional appli- cation notes. clock phase adjustment the pcm may be used to adjust the phase of the input clock. the result is an output clock which has its active edge either preceding or following the active edge of the input clock. clock phase adjustment is accom- plished in dll mode by delaying the clock. this is dis- cussed in the delay-locked loop (dll) mode section. examples of using the delayed clock as an early or late phase-adjusted clock are outlined in the following para- graphs. an output clock that precedes the input clock can be used to compensate for clock delay that is largely due to excessive loading. the preceding output clock is really not early relative to the input clock, but is delayed almost a full cycle. this is shown in figure 48a. the amount of delay that is being compensated for, plus clock setup time and some margin, is the amount less than one full clock cycle that the output clock is delayed from the input clock. in some systems, it is desirable to operate logic from several clocks that operate at different phases. this technique is often used in microprocessor-based sys- tems to transfer and process data synchronously between functional areas, but without incurring exces- sive delays. figure 48b shows an input clock and an output clock operating 180 out of phase. it also shows a version of the input clock that was shifted approxi- mately 180 using logic gates to create an inverter. note that the inverted clock is really shifted more than 180 due to the propagation delay of the inverter. the pcm output clock does not suffer from this delay. addi- tionally, the 180 shifted pcm output could be shifted by some smaller amount to effect an early 180 shifted clock that also accounts for loading effects. in terms of degrees of phase shift, the phase of a clock is adjustable in dll mode with resolution relative to the delay increment (see table 27): phase ad j ustment = ( dela y) * 11.25, dela y < 16 phase ad j ustment = (( dela y) * 11.25 ) C 360, dela y > 16 5-5979(f) figure 48. clock phase adjustment using the pcm input clock output clock input clock pcm output clock inverted input clock a. generating an early clock b. multiphase clock generation using the dll unintended phase shift due to inverter delay dll delay dll delay clock delay and setup being compensated
84 84 lucent technologies inc. data sheet june 1999 orca series 3c and 3t fpgas programmable clock manager (pcm) (continued) high-speed internal processing with slow i/os the pcm pll mode provides two outputs, one sent to the global system clock routing of the fpga and the other to the expressclk (s) that serve the fpga i/os. the expressclk output of the pcm has a divide capa- bility (div2) that the system clock output does not. this feature allows an input clock to be multiplied up to a higher frequency for high-speed internal processing, and also allows the expressclk output to be divided down to a lower frequency to accommodate off-fpga data transfers. for example, a 10 mhz input clock may be multiplied (see clock multiplication in the phase- locked loop (pll) mode subsection) to 25 mhz (div0 = 4, div1 = 5, div2 = 2) and output to the fpga expressclk . this allows the i/os of the circuit to run at 25 mhz ((2 * 5)/4 * 10 mhz). the system clock will run at div2 times the expressclk rate, which is 2 times 25 mhz, or 50 mhz. this setup allows for internal pro- cessing to occur at twice the rate of on/off device i/o transfers. pcm cautions cautions do apply when using the pcm . there are a number of configurations that are possible in the pcm that are theoretically valid, but may not produce viable results. this section describes some of those situa- tions, and should leave the user with an understanding of the types of pitfalls that must be avoided when modi- fying clock signals. resultant signals from the pcm must meet the fpga timing specifications. it is possible to specify pulses by using duty-cycle adjustments that are too narrow to function in the fpga. for instance, if a 40 mhz clock is doubled to 80 mhz and a 6.25% duty cycle is selected, the result will be a 780 ps pulse that repeats every 12.5 ns. this pulse falls outside of the clock pulse width specification and is not valid. using divider div2, it is possible to specify a clock mul- tiplication factor of 64 between the input clock and the output system clock. as mentioned above, the resultant frequency must meet all fpga timing specifications. the input clock must also meet the minimum specifica- tions. an input clock rate that is below the pcm clock minimum cannot be used even if the multiplied output is within the allowable range. the use of the pcm to tweak a clock signal to eliminate a particular problem, such as a single setup time viola- tion, is discouraged. a small shift in delay, duty cycle, or phase to correct a single-point problem is in essence an asynchronous patch to a synchronous system, mak- ing the system less stable. this type of local problem, as opposed to a global clock control issue like device- wide clock delay, can usually be eliminated through more robust design practices. if this type of change is made, the designer must be aware that depending on the extent of the change made, the design may fail to operate correctly in a different speed grade or voltage grade (e.g., 3c vs. 3t), or even in a different production lot of the same device. divider div2 is available in dll mode for the express- clk output, but its use is not recommended with duty- cycle adjusted clocks.
lucent technologies inc. 85 data sheet june 1999 orca series 3c and 3t fpgas fpga states of operation prior to becoming operational, the fpga goes through a sequence of states, including initialization, configura- tion, and start-up. figure 49 outlines these three fpga states. figure 49. fpga states of operation initialization upon powerup, the device goes through an initialization process. first, an internal power-on-reset circuit is trig- gered when power is applied. when v dd reaches the voltage at which portions of the fpga begin to operate (2.5 v to 3 v for the or3cxx, 2.2 v to 2.7 v for the or3txxx), the i/os are configured based on the con- figuration mode, as determined by the mode select inputs m[2:0]. a time-out delay is initiated when v dd reaches between 3.0 v and 4.0 v (or3cxx) or 2.7 v to 3.0 v (or3txxx) to allow the power supply voltage to stabilize. the init and done outputs are low. at pow- erup, if v dd does not rise from 2.0 v to v dd in less than 25 ms, the user should delay configuration by inputting a low into init , prgm , or reset until v dd is greater than the recommended minimum operating voltage (4.75 v for or3cxx commercial devices and 3.0 v for or3txxx devices). at the end of initialization, the default configuration option is that the configuration ram is written to a low state. this prevents shorts prior to configuration. as a configuration option, after the first configuration (i.e., at reconfiguration), the user can reconfigure without clearing the internal configuration ram first. the active-low, open-drain initialization signal init is released and must be pulled high by an external resis- tor when initialization is complete. to synchronize the configuration of multiple fpgas, one or more init pins should be wire-anded. if init is held low by one or more fpgas or an external device, the fpga remains in the initialization state. init can be used to signal that the fpgas are not yet initialized. after init goes high for two internal clock cycles, the mode lines (m[3:0]) are sampled, and the fpga enters the configuration state. the high during configuration (hdc), low during config- uration ( ldc ), and done signals are active outputs in the fpgas initialization and configuration states. hdc, ldc , and done can be used to provide control of external logic signals such as reset, bus enable, or prom enable during configuration. for parallel master configuration modes, these signals provide prom enable control and allow the data pins to be shared with user logic signals. 5-4529(f) C active i/o C release internal reset C done goes high start-up initialization configuration reset or prgm low prgm low C clear configuration C init low, hdc high, ldc low operation powerup C power-on time delay C m[3:0] mode is selected C configuration data frame C init high, hdc high, ldc low C dout active yes no no reset , init , or prgm low bit error yes written memory
86 86 lucent technologies inc. data sheet june 1999 orca series 3c and 3t fpgas fpga states of operation (continued) if configuration has begun, an assertion of reset or prgm initiates an abort, returning the fpga to the ini- tialization state. the prgm and reset pins must be pulled back high before the fpga will enter the config- uration state. during the start-up and operating states, only the assertion of prgm causes a reconfiguration. in the master configuration modes, the fpga is the source of configuration clock (cclk). in this mode, the initialization state is extended to ensure that, in daisy- chain operation, all daisy-chained slave devices are ready. independent of differences in clock rates, master mode devices remain in the initialization state an addi- tional six internal clock cycles after init goes high. when configuration is initiated, a counter in the fpga is set to 0 and begins to count configuration clock cycles applied to the fpga. as each configuration data frame is supplied to the fpga, it is internally assem- bled into data words. each data word is loaded into the internal configuration memory. the configuration load- ing process is complete when the internal length count equals the loaded length count in the length count field, and the required end of configuration frame is written. all or3cxx i/os operate as ttl inputs during configu- ration (or3txxx i/os are cmos-only). all i/os that are not used during the configuration process are 3-stated with internal pull-ups. warning : during configuration, all or3txxx inputs have internal pull-ups enabled. if these inputs are driven to 5v, they will draw substantial current ( @ 5 ma). this is due to the fact that the inputs are pulled up to 3v. during configuration, the pic and plc latches/ffs are held set/reset and the internal bidi buffers are 3- stated. the combinatorial logic begins to function as the fpga is configured. figure 50 shows the general waveform of the initialization, configuration, and start- up states. configuration the orca series fpga functionality is determined by the state of internal configuration ram. this configura- tion ram can be loaded in a number of different modes. in these configuration modes, the fpga can act as a master or a slave of other devices in the sys- tem. the decision as to which configuration mode to use is a system design issue. configuration is dis- cussed in detail, including the configuration data format and the configuration modes used to load the configu- ration data in the fpga, following a description of the start-up state. 5-4482(f) fi g ure 50. initialization/confi g uration/start-u p waveforms v dd m[3:0] cclk hdc ldc done user i/o internal reset (gsrn) configuration operation initialization start-up reset prgm init
lucent technologies inc. 87 data sheet june 1999 orca series 3c and 3t fpgas fpga states of operation (continued) start-up after configuration, the fpga enters the start-up phase. this phase is the transition between the config- uration and operational states and begins when the number of cclks received after init goes high is equal to the value of the length count field in the configuration frame and when the end of configuration frame has been written. the system design issue in the start-up phase is to ensure the user i/os become active without inadvertently activating devices in the system or caus- ing bus contention. a second system design concern is the timing of the release of global set/reset of the plc latches/ffs. there are configuration options that control the relative timing of three events: done going high, release of the set/reset of internal ffs, and user i/os becoming active. figure 51 shows the start-up timing for orca fpgas. the system designer determines the relative timing of the i/os becoming active, done going high, and the release of the set/reset of internal ffs. in the orca series fpga, the three events can occur in any arbitrary sequence. this means that they can occur before or after each other, or they can occur simulta- neously. there are four main start-up modes: cclk_nosync, cclk_sync, uclk_nosync, and uclk_sync. the only difference between the modes starting with cclk and those starting with uclk is that for the uclk modes, a user clock must be supplied to the start-up logic. the timing of start-up events is then based upon this user clock, rather than cclk. the dif- ference between the sync and nosync modes is that for sync mode, the timing of two of the start-up events, release of the set/reset of internal ffs, and the i/os becoming active is triggered by the rise of the external done pin followed by a variable number of ris- ing clock edges (either cclk or uclk). for the nosync mode, the timing of these two events is based only on either cclk or uclk. done is an open-drain bidirectional pin that may include an optional (enabled by default) pull-up resistor to accommodate wired anding. the open-drain done signals from multiple fpgas can be tied together (anded) with a pull-up (internal or external) and used as an active-high ready signal, an active-low prom enable, or a reset to other portions of the system. when used in sync mode, these anded done pins can be used to synchronize the other two start-up events, since they can all be synchronized to the same external signal. this signal will not rise until all fpgas release their done pins, allowing the signal to be pulled high. the default for orca is the cclk_sync synchro- nized start-up mode where done is released on the first cclk rising edge, c1 (see figure 51). since this is a synchronized start-up mode, the open-drain done signal can be held low externally to stop the occurrence of the other two start-up events. once the done pin has been released and pulled up to a high level, the other two start-up events can be programmed individu- ally to either happen immediately or after up to four ris- ing edges of cclk (di, di + 1, di + 2, di + 3, di + 4). the default is for both events to happen immediately after done is released and pulled high. a commonly used design technique is to release done one or more clock cycles before allowing the i/o to become active. this allows other configuration devices, such as proms, to be disconnected using the done signal so that there is no bus contention when the i/os become active. in addition to controlling the fpga during start-up, other start-up techniques that avoid contention include using isolation devices between the fpga and other circuits in the system, reassigning i/o locations, and maintaining i/os as 3- stated outputs until contentions are resolved. each of these start-up options can be selected during bit stream generation in orca foundry, using advanced options. for more information, please see the orca foundry documentation.
88 88 lucent technologies inc. data sheet june 1999 orca series 3c and 3t fpgas fpga states of operation (continued) note: f = finished, no more clks required. 5-2761(f) figure 51. start-up waveforms reconfiguration to reconfigure the fpga when the device is operating in the system, a low pulse is input into prgm . the con- figuration data in the fpga is cleared, and the i/os not used for configuration are 3-stated. the fpga then samples the mode select inputs and begins reconfigu- ration. when reconfiguration is complete, done is released, allowing it to be pulled high. partial reconfiguration all orca device families have been designed to allow a partial reconfiguration of the fpga at any time. this is done by setting a bit stream option in the previous configuration sequence that tells the fpga to not reset all of the configuration ram during a reconfiguration. then only the configuration frames that are to be modi- fied need to be rewritten, thereby reducing the configu- ration time. other bit stream options are also available that allow one portion of the fpga to remain in operation while a partial reconfiguration is being done. if this is done, the user must be careful to not cause contention between the two configurations (the bit stream resident in the fpga and the partial reconfiguration bit stream) as the second reconfiguration bit stream is being loaded. other configuration options there are many other configuration options available to the user that can be set during bit stream generation in orca foundry. these include options to enable boundary scan and/or the microprocessor interface ( mpi ) and/or the programmable clock manager ( pcm ), readback options, and options to control and use the internal oscillator after configuration. other useful options that affect the next configuration (not the current configuration process) include options to disable the global set/reset during configuration, dis- able the 3-state of i/os during configuration, and dis- able the reset of internal rams during configuration to allow for partial configurations (see above). for more information on how to set these and other configuration options, please see the orca foundry documenta- tion. di c1 c2 c3 c4 f c1 c2 c3 c4 c1 c2 c3 c4 c1, c2, c3, or c4 di + 1 di di + 2 di + 3 di + 4 di + 1 di di + 2 di + 3 di + 4 cclk_sync done in u1 u2 u3 u4 f u1 u2 u3 u4 u1 u2 u3 u4 uclk_nosync di + 1 di di + 2 di + 3 di + 4 di + 1 di + 2 di + 3 uclk_sync uclk period synchronization uncertainty done in f c1 c1 u1, u2, u3, or u4 done i/o gsrn active done i/o gsrn active done i/o gsrn active done i/o gsrn active uclk f cclk_nosync
lucent technologies inc. 89 data sheet june 1999 orca series 3c and 3t fpgas configuration data format the orca foundry development system interfaces with front-end design entry tools and provides tools to produce a fully configured fpga. this section dis- cusses using the orca foundry development system to generate configuration ram data and then provides the details of the configuration frame format. the orca or3cxx and or3txxx series fpgas are bit stream compatible. using orca foundry to generate configuration ram data the configuration data bit stream defines the i/o func- tionality, logic, and interconnections within the fpga. the bit stream is generated by the development sys- tem. the bit stream created by the bit stream genera- tion tool is a series of 1s and 0s used to write the fpga configuration ram. it can be loaded into the fpga using one of the configuration modes discussed later. in the bit stream generator, the designer selects options that affect the fpgas functionality. using the output of the bit stream generator, circuit_name.bit , the development systems download tool can load the configuration data into the orca series fpga evalua- tion board from a pc or workstation. alternatively, a user can program a prom (such as a serial rom or a standard eprom) and load the fpga from the prom. the development systems prom programming tool produces a file in .mks or .exo for- mat. configuration data frame configuration data can be presented to the fpga in two frame formats: autoincrement and explicit. a detailed description of the frame formats is shown in figure 52, figure 53, and table 32. the two modes are similar except that autoincrement mode uses assumed address incrementation to reduce the bit stream size, and explicit mode requires an address for each data frame. in both cases, the header frame begins with a series of 1s and a preamble of 0010, followed by a 24-bit length count field representing the total number of configuration clocks needed to complete the loading of the fpgas. following the header frame is a mandatory id frame. (note that the id frame was optional in the orca 2c and 2c/txxa series.) the id frame contains data used to determine if the bit stream is being loaded to the correct type of orca fpga (i.e., a bit stream generated for an or3c55 is being sent to an or3c55). error checking is always enabled for series 3 devices, through the use of an 8-bit checksum. one bit in the id frame also selects between the autoincrement and explicit address modes for this load of the configuration data. a configuration data frame follows the id frame. a data frame starts with a 01-start bit pair and ends with enough 1-stop bits to reach a byte boundary. if using autoincrement configuration mode, subsequent data frames can follow. if using explicit mode, one or more address frames must follow each data frame, telling the fpga at what addresses the preceding data frame is to be stored (each data frame can be sent to multiple addresses). following all data and address frames is the postam- ble. the format of the postamble is the same as an address frame with the highest possible address value with the checksum set to all ones.
90 lucent technologies inc. data sheet june 1999 orca series 3c and 3t fpgas configuration data format (continued) 5-5759(f) figure 52. serial configuration data formatautoincrement mode 5-5760(f) figure 53. serial configuration data formatexplicit mode table 32. confi g uration frame format and contents * in mpi confi g uration mode, the number of stop bits = 32. note: for slave parallel mode, the b y te containin g the preamble must be 11110010. the number of leadin g header dumm y bits must be ( n * 8 ) + 4, where n is an y nonne g ative inte g er and the number of trailin g dumm y bits must be ( n * 8 ) , where n is an y positive inte g er. the number of stop bits/frame for slave parallel mode must be ( x * 8 ) , where x is a positive inte g er. note also that the bit stream g enerator tool supplies a bit stream that is compatible with all confi g uration modes, includin g slave parallel mode. header 11110010 preamble 24-bit len g th count confi g uration frame len g th. 11111111 trailin g header8 bits. id frame 0101 1111 1111 1111 id frame header. confi g uration mode 00 = autoincrement, 01 = explicit. reserved [ 41:0 ] reserved bits set to 0. id 20-bit part id. checksum 8-bit checksum. 11111111 ei g ht stop bits ( hi g h ) to separate frames. confi g uration data frame ( repeated for each data frame ) 01 data frame header. data bits number of data bits depends upon device. ali g nment bits = 0 strin g of 0 bits added to bit stream to make frame header, plus data bits reach a b y te boundar y . checksum 8-bit checksum. 11111111 ei g ht stop bits ( hi g h ) to separate frames. confi g uration address frame 00 address frame header. 14 address bits 14-bit address of location to start data stora g e. checksum 8-bit checksum. 11111111 ei g ht stop bits ( hi g h ) to separate frames. postamble 00 postamble header. 11111111 111111 dumm y address. 1111111111111111 16 stop bits.* configuration data configuration data 10 01 01 preamble length id frame configuration configuration postamble configuration header 00 00 count data frame 1 data frame 2 preamble length id frame configuration configuration postamble configuration header address address 00 count data frame 1 data frame 2 frame 2 frame 1 configuration data configuration data 10 01 01 00 00 00
lucent technologies inc. 91 data sheet june 1999 orca series 3c and 3t fpgas configuration data format (continued) the length and number of data frames and information on the prom size for the series 3 fpgas are given in table 33. table 33 . confi g uration frame size bit stream error checking there are three different types of bit stream error checking performed in the orca series 3 fpgas: id frame, frame alignment, and crc checking. the id data frame is sent to a dedicated location in the fpga. this id frame contains a unique code for the device for which it was generated. this device code is compared to the internal code of the fpga. any differences are flagged as an id error. this frame is automatically created by the bit stream generation program in orca foundry. each data and address frame in the fpga begins with a frame start pair of bits and ends with eight stop bits set to 1. if any of the previous stop bits were a 0 when a frame start pair is encountered, it is flagged as a frame align- ment error. error checking is also done on the fpga for each frame by means of a checksum byte. if an error is found on eval- uation of the checksum byte, then a checksum/parity error is flagged. the checksum is the xor of all the data bytes, from the start of frame up to and including the bytes before the checksum. it applies to the id, address, and data frames. when any of the three possible errors occur, the fpga is forced into an idle state, forcing init low. the fpga will remain in this state until either the reset or prgm pins are asserted. if using either of the mpi modes to configure the fpga, the specific type of bit stream error is written to one of the mpi registers by the fpga configuration logic. the pgrm bit of the mpi control register can also be used to reset out of the error condition and restart configuration. devices or3t20 or3t30 or3c/t55 or3c/t80 or3t125 # of frames 856 984 1240 1496 1880 data bits/frame 202 232 292 352 442 confi g uration data ( # of frames x # of data bits/frame ) 172,912 228,288 362,080 526,592 830,960 maximum total # bits/frame ( ali g n bits, 01 frame start, 8-bit checksum, 8 stop bits ) 224 256 312 376 464 maximum confi g uration data ( # bits/frame x # of frames ) 191,744 251,904 386,880 562,496 872,320 maximum prom size ( bits ) ( add confi g uration header and postamble ) 191,912 252,072 387,048 562,664 872,488
92 92 lucent technologies inc. data sheet june 1999 orca series 3c and 3t fpgas fpga configuration modes there are eight methods for configuring the fpga. seven of the configuration modes are selected on the m0, m1, and m2 inputs. the eighth configuration mode is accessed through the boundary-scan interface. a fourth input, m3, is used to select the frequency of the internal oscillator, which is the source for cclk in some configuration modes. the nominal frequencies of the internal oscillator are 1.25 mhz and 10 mhz. the 1.25 mhz frequency is selected when the m3 input is unconnected or driven to a high state. there are three basic fpga configuration modes: master, slave, and peripheral. the configuration data can be transmitted to the fpga serially or in parallel bytes. as a master, the fpga provides the control sig- nals out to strobe data in. as a slave device, a clock is generated externally and provided into the cclk input. in the three peripheral modes, the fpga acts as a microprocessor peripheral. table 34 lists the functions of the configuration mode pins. note that two configura- tion modes previously available on the or2cxx and or2c/txxa devices (master parallel down and syn- chronous peripheral) have been removed for series 3 devices. table 34. confi g uration modes * motorola is a re g istered trademark of motorola, inc. master parallel mode the master parallel configuration mode is generally used to interface to industry-standard, byte-wide mem- ory, such as the 2764 and larger eproms. figure 54 provides the connections for master parallel mode. the fpga outputs an 18-bit address on a[17:0] to memory and reads 1 byte of configuration data on the rising edge of rclk. the parallel bytes are internally serial- ized starting with the least significant bit, d0. d[7:0] of the fpga can be connected to d[7:0] of the micropro- cessor only if a standard prom file format is used. if a .bit or .rbt file is used from orca foundry, then the user must mirror the bytes in the .bit or .rbt file or leave the .bit or .rbt file unchanged and connect d[7:0] of the fpga to d[0:7] of the microprocessor. figure 54. master parallel configuration schematic in master parallel mode, the starting memory address is 00000 hex, and the fpga increments the address for each byte loaded. one master mode fpga can interface to the memory and provide configuration data on dout to additional fpgas in a daisy-chain. the configuration data on dout is provided synchronously with the falling edge of cclk. the frequency of the cclk output is eight times that of rclk. m2 m1 m0 cclk confi g uration mode data 0 0 0 output master serial serial 0 0 1 input slave parallel parallel 0 1 0 output microprocessor: motorola * pow- erpc parallel 0 1 1 output microprocessor: intel i960 parallel 1 0 0 output master parallel parallel 101outputas y nc peripheral parallel 110 reserved 1 1 1 input slave serial serial eprom a[17:0] done m2 m1 m0 hdc orca series fpga rclk ldc v dd d[7:0] dout cclk to daisy- chained devices v dd or gnd prgm program a[17:0] d[7:0] oe ce
lucent technologies inc. 93 data sheet june 1999 orca series 3c and 3t fpgas fpga configuration modes (continued) master serial mode in the master serial mode, the fpga loads the configu- ration data from an external serial rom. the configura- tion data is either loaded automatically at start-up or on a prgm command to reconfigure. the att1700a series serial proms can be used to configure the fpga in the master serial mode. this provides a sim- ple 4-pin interface in a compact package. configuration in the master serial mode can be done at powerup and/or upon a configure command. the sys- tem or the fpga must activate the serial rom's reset /oe and ce inputs. at powerup, the fpga and serial rom each contain internal power-on reset cir- cuitry that allows the fpga to be configured without the system providing an external signal. the power-on reset circuitry causes the serial rom's internal address pointer to be reset. after powerup, the fpga automati- cally enters its initialization phase. the serial rom/fpga interface used depends on such factors as the availability of a system reset pulse, avail- ability of an intelligent host to generate a configure command, whether a single serial rom is used or mul- tiple serial roms are cascaded, whether the serial rom contains a single or multiple configuration pro- grams, etc. because of differing system requirements and capabilities, a single fpga/serial rom interface is generally not appropriate for all applications. data is read in the fpga sequentially from the serial rom. the data output from the serial rom is con- nected directly into the din input of the fpga. the cclk output from the fpga is connected to the clk input of the serial rom. during the configuration pro- cess, cclk clocks one data bit on each rising edge. since the data and clock are direct connects, the fpga/serial rom design task is to use the system or fpga to enable the reset /oe and ce of the serial rom(s). there are several methods for enabling the serial roms reset /oe and ce inputs. the serial roms reset /oe is programmable to function with reset active-high and oe active-low or reset active- low and oe active-high. in figure 55, serial roms are cascaded to configure multiple daisy-chained fpgas. the host generates a 500 ns low pulse into the fpga's prgm input. the fpgas init input is connected to the serial roms reset /oe input, which has been programmed to function with reset active-low and oe active-high. the fpga done is routed to the ce pin. the low on done enables the serial roms. at the completion of configuration, the high on the fpga's done disables the serial rom. serial roms can also be cascaded to support the con- figuration of multiple fpgas or to load a single fpga when configuration data requirements exceed the capacity of a single serial rom. after the last bit from the first serial rom is read, the serial rom outputs ceo low and 3-states the data output. the next serial rom recognizes the low on ce input and outputs con- figuration data on the data output. after configuration is complete, the fpgas done output into ce disables the serial roms. this fpga/serial rom interface is not used in applica- tions in which a serial rom stores multiple configura- tion programs. in these applications, the next configuration program to be loaded is stored at the rom location that follows the last address for the previ- ous configuration program. the reason the interface in figure 55 will not work in this application is that the low output on the init signal would reset the serial rom address pointer, causing the first configuration to be reloaded. in some applications, there can be contention on the fpga's din pin. during configuration, din receives configuration data, and after configuration, it is a user i/o. if there is contention, an early done at start-up (selected in orca foundry) may correct the problem. an alternative is to use ldc to drive the serial rom's ce pin. in order to reduce noise, it is generally better to run the master serial configuration at 1.25 mhz (m3 pin tied high), rather than 10 mhz, if possible. figure 55. master serial configuration schematic att1700a din m2 m1 m0 orca series fpga cclk dout to daisy- chained devices data clk ce ceo att1700a data clk reset /oe ceo ce to more serial roms as needed done init program reset /oe prgm 5-4456.1(f)
94 94 lucent technologies inc. data sheet june 1999 orca series 3c and 3t fpgas fpga configuration modes (continued) asynchronous peripheral mode figure 56 shows the connections needed for the asyn- chronous peripheral mode. in this mode, the fpga system interface is similar to that of a microprocessor- peripheral interface. the microprocessor generates the control signals to write an 8-bit byte into the fpga. the fpga control inputs include active-low cs0 and active- high cs1 chip selects and wr and rd inputs. the chip selects can be cycled or maintained at a static level during the configuration cycle. each byte of data is writ- ten into the fpgas d[7:0] input pins. d[7:0] of the fpga can be connected to d[7:0] of the microproces- sor only if a standard prom file format is used. if a .bit or .rbt file is used from orca foundry, then the user must mirror the bytes in the .bit or .rbt file or leave the .bit or .rbt file unchanged and connect d[7:0] of the fpga to d[0:7] of the microprocessor. the fpga provides an rdy/ busy status output to indi- cate that another byte can be loaded. a low on rdy/ busy indicates that the double-buffered hold/shift reg- isters are not ready to receive data, and this pin must be monitored to go high before another byte of data can be written. the shortest time rdy/ busy is low occurs when a byte is loaded into the hold register and the shift register is empty, in which case the byte is immediately transferred to the shift register. the long- est time for rdy/ busy to remain low occurs when a byte is loaded into the holding register and the shift register has just started shifting configuration data into configuration ram. the rdy/ busy status is also available on the d7 pin by enabling the chip selects, setting wr high, and apply- ing rd low, where the rd input provides an output enable for the d7 pin when rd is low. the d[6:0] pins are not enabled to drive when rd is low and, therefore, only act as input pins in asynchronous peripheral mode. optionally, the user can ignore the rdy/ busy status and simply wait until the maximum time it would take for the rdy/ busy line to go high, indicating the fpga is ready for more data, before writing the next data byte. figure 56. asynchronous peripheral configuration microprocessor interface (mpi) mode the built-in mpi in series 3 fpgas is designed for use in configuring the fpga. figure 57 and figure 58 show the glueless interface for fpga configuration and read- back from the powerpc and i960 processors, respec- tively. when enabled by the mode pins, the mpi handles all configuration/readback control and hand- shaking with the host processor. for single fpga con- figuration, the host sets the configuration control register prgm bit to zero then back to a one and, after reading that the init signal is high in the mpi status register, transfers data 8 bits at a time to the fpgas d[7:0] input pins. if configuring multiple fpgas through daisy-chain operation is desired, the mp_daisy bit must be set in the configuration control register of the mpi . because of the latency involved in a daisy-chain configuration, the mp_hold_bus bit may be set to zero rather than one for daisy-chain operation. this allows the mpi to acknowledge the data transfer before the configuration information has been serialized and transferred on the fpga daisy-chain. the early acknowledgment frees the host processor to perform other system tasks. con- figuring with the mp_hold_bus bit at zero requires that the host microprocessor poll the rdy/ busy bit of the mpi status register and/or use the mpi interrupt capability to confirm the readiness of the mpi for more configuration data. micro- processor d[7:0] cs1 m2 m1 m0 hdc orca series fpga 8 ldc v dd done cs0 dout cclk to daisy- chained devices bus controller address decode logic rd wr rdy/busy init prgm
lucent technologies inc. 95 data sheet june 1999 orca series 3c and 3t fpgas fpga configuration modes (continued) there are two options for using the host interrupt request in configuration mode. the configuration con- trol register offers control bits to enable the interrupt on either a bit stream error or to notify the host processor when the fpga is ready for more configuration data. the mpi status register may be used in conjunction with, or in place of, the interrupt request options. the status register contains a 2-bit field to indicate the bit stream error status. as previously mentioned, there is also a bit to indicate the mpi s readiness to receive another byte of configuration data. a flow chart of the mpi configuration process is shown in figure 59. the mpi status and configuration register bit maps can be found in the special function blocks section and mpi configuration timing information is available in the tim- ing characteristics section of this data sheet. 5-5761(f) note: fpga shown as a memor y -mapped peripheral usin g cs0 and cs1. other decodin g schemes are possible usin g cs0 and/or cs1. figure 57. powerpc /mpi configuration schematic 5-5762(f) note: fpga shown as onl y s y stem peripheral with fixed chip select si g nals. for multiperipheral s y stems, address decodin g and/ or latchin g can be used to implement chip selects. figure 58. i960 /mpi configuration schematic configuration readback can also be performed via the mpi when it is in user mode. the mpi is enabled in user mode by setting the mp_user bit to 1 in the configura- tion control register prior to the start of configuration or through a configuration option. to perform readback, the host processor writes the 14-bit readback start address to the readback address registers and sets the rd_cfg bit to 0 in the configuration control register. readback data is returned 8 bits at a time to the read- back data register and is valid when the data_rdy bit of the status register is 1. there is no error checking during readback. a flow chart of the mpi readback operation is shown in figure 60. the rd_data pin used for dedicated fpga readback is invalid during mpi readback. 5-5763(f) figure 59. configuration through mpi dout cclk d[7:0] a[4:0] mpi_clk mpi_rw mpi_ack mpi_bi mpi_irq mpi_strb cs0 cs1 hdc ldc d[7:0] a[27:31] clkout rd/wr ta bi irq x ts a26 a25 to daisy- chained devices powerpc orca 8 fpga series 3 done init dout cclk d[7:0] mpi_clk mpi_rw mpi_ack mpi_irq mpi_ale mpi_be1 hdc ldc to daisy- chained devices orca 8 fpga series 3 done init ad[7:0] clkin w/r rdyrcv xint x ale be1 i960 cs1 cs0 i960 system clock v dd mpi_be0 be0 mpi_strb ads power on with write configuration read status register init = 1? no read status register bit stream error? data_rdy = 1? write data to done = 1? done error yes yes yes no no yes no valid m[3:0] control register bits configuration data reg
96 lucent technologies inc. data sheet june 1999 orca series 3c and 3t fpgas fpga configuration modes (continued) 5-5764(f) figure 60. readback through mpi enable microprocessor set readback address write rd_cfg to 0 data_rdy = 1? read data register start of frame data = 0xff? yes yes read status register in control register 1 interface in user mode read data register found? read until end of frame finished readback? yes yes write rd_cfg control stop no no error no error no read data register data = 0xff? yes no error to 1 in register 1
lucent technologies inc. 97 data sheet june 1999 orca series 3c and 3t fpgas fpga configuration modes (continued) slave serial mode the slave serial mode is primarily used when multiple fpgas are configured in a daisy-chain (see the daisy- chaining section). it is also used on the fpga evalua- tion board that interfaces to the download cable. a device in the slave serial mode can be used as the lead device in a daisy-chain. figure 61 shows the connec- tions for the slave serial configuration mode. the configuration data is provided into the fpgas din input synchronous with the configuration clock cclk input. after the fpga has loaded its configuration data, it retransmits the incoming configuration data on dout. cclk is routed into all slave serial mode devices in parallel. multiple slave fpgas can be loaded with identical con- figurations simultaneously. this is done by loading the configuration data into the din inputs in parallel. 5-4485(f) figure 61. slave serial configuration schematic slave parallel mode the slave parallel mode is essentially the same as the slave serial mode except that 8 bits of data are input on pins d[7:0] for each cclk cycle. due to 8 bits of data being input per cclk cycle, the dout pin does not contain a valid bit stream for slave parallel mode. as a result, the lead device cannot be used in the slave parallel mode in a daisy-chain configuration. figure 62 is a schematic of the connections for the slave parallel configuration mode. wr and cs0 are active-low chip select signals, and cs1 is an active- high chip select signal. these chip selects allow the user to configure multiple fpgas in slave parallel mode using an 8-bit data bus common to all of the fpgas. these chip selects can then be used to select the fpga(s) to be configured with a given bit stream. the chip selects must be active for each valid cclk cycle until the device has been completely pro- grammed. they can be inactive between cycles but must meet the setup and hold times for each valid pos- itive cclk. d[7:0] of the fpga can be connected to d[7:0] of the microprocessor only if a standard prom file format is used. if a .bit or .rbt file is used from orca foundry, then the user must mirror the bytes in the .bit or .rbt file or leave the .bit or .rbt file unchanged and connect d[7:0] of the fpga to d[0:7] of the microprocessor. 5-4487(f) figure 62. slave parallel configuration schematic micro- processor or download cable m2 m1 m0 hdc series fpga ldc v dd cclk prgm dout to daisy- chained devices done din init orca micro- processor or system d[7:0] done cclk cs1 m2 m1 m0 hdc ldc 8 v dd init prgm cs0 wr series fpga orca
98 98 lucent technologies inc. data sheet june 1999 orca series 3c and 3t fpgas fpga configuration modes (continued) daisy-chaining multiple fpgas can be configured by using a daisy- chain of the fpgas. daisy-chaining uses a lead fpga and one or more fpgas configured in slave serial mode. the lead fpga can be configured in any mode except slave parallel mode. (daisy-chaining is available with the boundary-scan ram_w instruction discussed later.) all daisy-chained fpgas are connected in series. each fpga reads and shifts the preamble and length count in on positive cclk and out on negative cclk edges. an upstream fpga that has received the preamble and length count outputs a high on dout until it has received the appropriate number of data frames so that downstream fpgas do not receive frame start bit pairs. after loading and retransmitting the preamble and length count to a daisy-chain of slave devices, the lead device loads its configuration data frames. the loading of configuration data continues after the lead device has received its configuration data if its internal frame bit counter has not reached the length count. when the configuration ram is full and the num- ber of bits received is less than the length count field, the fpga shifts any additional data out on dout. the configuration data is read into din of slave devices on the positive edge of cclk, and shifted out dout on the negative edge of cclk. figure 63 shows the connections for loading multiple fpgas in a daisy- chain configuration. the generation of cclk for the daisy-chained devices that are in slave serial mode differs depending on the configuration mode of the lead device. a master paral- lel mode device uses its internal timing generator to produce an internal cclk at eight times its memory address rate (rclk). the asynchronous peripheral mode device outputs eight cclks for each write cycle. if the lead device is configured in slave mode, cclk must be routed to the lead device and to all of the daisy-chained devices. 5-4488(f figure 63. daisy-chain configuration schematic as seen in figure 63, the init pins for all of the fpgas are connected together. this is required to guarantee that powerup and initialization will work correctly. in general, the done pins for all of the fpgas are also connected together as shown to guarantee that all of the fpgas enter the start-up state simultaneously. this may not be required, depending upon the start-up sequence desired. v dd eprom program d[7:0] oe ce a[17:0] a[17:0] d[7:0] done m2 m1 m0 done hdc ldc rclk cclk dout din dout din cclk done dout init init init cclk v dd v dd or gnd prgm prgm m2 m1 m0 prgm m2 m1 m0 v dd v dd hdc ldc rclk hdc ldc rclk v dd orca series fpga slave #2 orca series fpga master orca series fpga slave #1
lucent technologies inc. 99 data sheet june 1999 orca series 3c and 3t fpgas fpga configuration modes (continued) daisy-chaining with boundary scan multiple fpgas can be configured through the jtag ports by using a daisy-chain of the fpgas. this daisy-chain- ing operation is available upon initial configuration after powerup, after a power-on reset, after pulling the program pin to reset the chip, or during a reconfiguration if the en_jtag ram has been set. all daisy-chained fpgas are connected in series. each fpga reads and shifts the preamble and length count in on the positive tck and out on the negative tck edges. an upstream fpga that has received the preamble and length count outputs a high on tdo until it has received the appropriate number of data frames so that downstream fpgas do not receive frame start bit pairs. after load- ing and retransmitting the preamble and length count to a daisy-chain of downstream devices, the lead device loads its configuration data frames. the loading of configuration data continues after the lead device had received its configuration read into tdi of downstream devices on the positive edge of tck, and shifted out tdo on the negative edge of tck. figure 63 shows the connections for loading multiple fpgas in a jtag daisy-chain configuration.
100 lucent technologies inc. data sheet june 1999 orca series 3c and 3t fpgas absolute maximum ratings stresses in excess of the absolute maximum ratings can cause permanent damage to the device. these are abso- lute stress ratings only. functional operation of the device is not implied at these or any other conditions in excess of those given in the operations sections of this data sheet. exposure to absolute maximum ratings for extended periods can adversely affect device reliability. the orca series fpgas include circuitry designed to protect the chips from damaging substrate injection cur- rents and to prevent accumulations of static charge. nevertheless, conventional precautions should be observed during storage, handling, and use to avoid exposure to excessive electrical stress. table 35. absolute maximum ratings recommended operating conditions table 36. recommended operating conditions note: the maximum recommended j unction temperature ( t j ) durin g operation is 125 c. parameter s y mbol min max unit stora g e temperature t st g C65 150 c suppl y volta g e with respect to ground v dd C0.5 7.0 v input si g nal with respect to ground C0.5 v dd + 0.3 v si g nal applied to hi g h-impedance output C0.5 v dd + 0.3 v maximum packa g e bod y temperature 220 c mode or3cxx or3txxx tem p erature ran g e ( ambient ) su pp l y volta g e ( v dd ) tem p erature ran g e ( ambient ) su pp l y volta g e ( v dd ) commercial 0 c to 70 c 5 v 5% 0 c to 70 c 3.0 v to 3.6 v industrial C40 c to +85 c 5 v 10% C40 c to +85 c 3.0 v to 3.6 v
lucent technologies inc. 101 data sheet june 1999 orca series 3c and 3t fpgas electrical characteristics table 37 . electrical characteristics or3cxx commercial: v dd = 5.0 v 5%, 0 c < t a < 70 c; industrial: v dd = 5.0 v 10%, C40 c < t a < +85 c. or3txxx commercial: v dd = 3.0 v to 3.6 v, 0 c < t a < 70 c; industrial: v dd = 3.0 v to 3.6 v, C40 c < t a < +85 c . parameter s y m- bol test conditions or3cxx or3txxx unit min max min max input volta g e: hi g h low v ih v il input confi g ured as cmos ( includes or3txxx ) 50% v dd gnd C 0.5 v dd + 0.5 20% v dd 50% v dd gnd C 0.5 v dd + 0.5 30% v dd v v input volta g e: hi g h low v ih v il or3txxx 5 v tolerant 50% v dd gnd C 0.5 5.8 v 30% v dd v v input volta g e: hi g h low v ih v il input confi g ured as ttl ( not valid for or3txxx ) 2.0 C0.5 v dd + 0.3 0.8 v v output volta g e: hi g h low v oh v ol v dd = min, i oh = 6 ma or 3 ma v dd = min, i ol = 12 ma or 6 ma 2.4 0.4 2.4 0.4 v v input leaka g e current i l v dd = max, v in = v ss or v dd C10 10 C10 10 a standb y current: or3t20 or3t30 or3c/t55 or3c/t80 or3t125 i ddsb or3cxx ( t a = 25 c, v dd = 5.0 v ) or3txxx ( t a = 25 c, v dd = 3.3 v ) internal oscillator runnin g , no out- put loads, inputs v dd or gnd ( after confi g uration ) 4.06 4.56 4.70 4.90 5.30 5.80 6.70 ma ma ma ma ma standb y current: or3t20 or3t30 or3c/t55 or3c/t80 or3t125 i ddsb or3cxx ( t a = 25 c, v dd = 5.0 v ) or3txxx ( t a = 25 c, v dd = 3.3 v ) internal oscillator stopped, no output loads, inputs v dd or gnd ( after confi g uration ) 3.05 3.42 3.52 3.68 3.98 4.35 5.02 ma ma ma ma ma powerup current: or3t20 or3t30 or3c/t55 or3c/t80 or3t125 ipp power suppl y current @ approxi- matel y 1 v, within a recommended power suppl y ramp rate of 1 ms200 ms 3.2 5.4 1.2 1.6 2.7 4.0 6.5 ma ma ma ma ma data retention volta g ev dr t a = 25 c 2.3 2.3 v input capacitance c in or3cxx ( t a = 25 c, v dd = 5.0 v ) or3txxx ( t a = 25 c, v dd = 3.3 v ) test fre q uenc y = 1 mhz 9 8pf output capacitance c out or3cxx ( t a = 25 c, v dd = 5.0 v ) or3txxx ( t a = 25 c, v dd = 3.3 v ) test fre q uenc y = 1 mhz 9 8pf
102 lucent technologies inc. data sheet june 1999 orca series 3c and 3t fpgas electrical characteristics (continued) table 37. electrical characteristics (continued) or3cxx commercial: v dd = 5.0 v 5%, 0 c < t a < 70 c; industrial: v dd = 5.0 v 10%, C40 c < t a < +85 c. or3txxx commercial: v dd = 3.0 v to 3.6 v, 0 c < t a < 70 c; industrial: v dd = 3.0 v to 3.6 v, C40 c < t a < +85 c. * on the or3txxx devices, the pull-up resistor will externall y pull the pin to a level 1.0 v below v dd . note: for 3t devices driven to 5 v. parameter s y mbol test conditions or3cxx or3txxx unit min max min max done pull-up resistor* r done 100 100 k w m [ 3:0 ] pull-up resistors* r m 100 100 k w i/o pad static pull-up current* i pu or3cxx ( v dd = 5.25 v, v in = v ss , t a = 0 c ) or3txxx ( v dd = 3.6 v, v in = v ss , t a = 0 c ) 14.4 50.9 14.4 50.9 a i/o pad static pull-down current i pd or3cxx ( v dd = 5.25 v, v in = v ss , t a = 0 c ) or3txxx ( v dd = 3.6 v, v in = v ss , t a = 0 c ) 26 103 26 103 a i/o pad pull-up resistor* r pu v dd = all, v in = v ss , t a = 0 c 100 100 k w i/o pad pull-down resistor r pd v dd = all, v in = v dd , t a = 0 c 50 50 k w
lucent technologies inc. 103 data sheet june 1999 orca series 3c and 3t fpgas timing characteristics description to define speed grades, the orca series part number designation (see ordering information) uses a single- digit number to designate a speed grade. this number is not related to any single ac parameter. higher num- bers indicate a faster set of timing parameters. the actual speed sorting is based on testing the delay in a path consisting of an input buffer, combinatorial delay through all plcs in a row, and an output buffer. other tests are then done to verify other delay parameters, such as routing delays, setup times to ffs, etc. the most accurate timing characteristics are reported by the timing analyzer in the orca foundry develop- ment system. a timing report provided by the develop- ment system after layout divides path delays into logic and routing delays. the timing analyzer can also pro- vide logic delays prior to layout. while this allows rout- ing budget estimates, there is wide variance in routing delays associated with different layouts. the logic timing parameters noted in the electrical characteristics section of this data sheet are the same as those in the design tools. in the pfu timing given in table 41table 48, symbol names are generally a concatenation of the pfu operating mode (as defined in table 3) and the parameter type. the setup, hold, and propagation delay parameters, defined below, are designated in the symbol name by the set, hld, and del characters, respectively. the values given for the parameters are the same as those used during production testing and speed bin- ning of the devices. the junction temperature and sup- ply voltage used to characterize the devices are listed in the delay tables. actual delays at nominal tempera- ture and voltage for best-case processes can be much better than the values given. it should be noted that the junction temperature used in the tables is generally 85 c. the junction temperature for the fpga depends on the power dissipated by the device, the package thermal characteristics ( q ja ), and the ambient temperature, as calculated in the following equation and as discussed further in the package thermal characteristics section: t jmax = t amax + ( p ? q ja ) c note : the user must determine this j unction tempera- ture to see if the dela y s from orca foundr y should be derated based on the followin g derat- in g tables. table 38 and table 39 provide approximate power sup- ply and junction temperature derating for or3cxx com- mercial and industrial devices. table 40 provides the same information for the or3txxx devices (both com- mercial and industrial). the delay values in this data sheet and reported by orca foundry are shown as 1.00 in the tables. the method for determining the maximum junction temperature is defined in the pack- age thermal characteristics section. taken cumula- tively, the range of parameter values for best-case vs. worst-case processing, supply voltage, and junction temperature can approach 3 to 1. table 38 . deratin g for commercial devices ( or3cxx ) table 39 . deratin g for industrial devices ( or3cxx ) table 40. deratin g for commercial/industrial devices ( or3txxx ) note: the deratin g tables shown above are for a t y pical critical path that contains 33% lo g ic dela y and 66% routin g dela y . since the routin g dela y derates at a hi g her rate than the lo g ic dela y , paths with more than 66% routin g dela y will derate at a hi g her rate than shown in the table. the approximate deratin g values vs. temperature are 0.26% per c for lo g ic dela y and 0.45% per c for routin g dela y . the approximate deratin g values vs. volta g e are 0.13% per mv for both lo g ic and routin g dela y s at 25 c. t j ( c ) power su pp l y volta g e 4.75 v 5.0 v 5.25 v 0 0.81 0.79 0.77 25 0.85 0.83 0.81 85 1.00 0.97 0.95 100 1.05 1.02 1.00 125 1.12 1.09 1.07 t j ( c ) power su pp l y volta g e 4.5 v 4.75 v 5.0 v 5.25 v 5.5 v C40 0.71 0.70 0.68 0.66 0.65 0 0.80 0.78 0.76 0.74 0.73 25 0.84 0.82 0.80 0.78 0.77 85 1.00 0.97 0.94 0.93 0.91 100 1.05 1.01 0.99 0.97 0.95 125 1.12 1.09 1.06 1.04 1.02 t j ( c ) power su pp l y volta g e 3.0 v 3.3 v 3.6 v C40 0.73 0.66 0.61 0 0.82 0.73 0.68 25 0.87 0.78 0.72 85 1.00 0.90 0.83 100 1.04 0.94 0.87 125 1.10 1.00 0.92
104 104 lucent technologies inc. data sheet june 1999 orca series 3c and 3t fpgas timing characteristics (continued) in addition to supply voltage, process variation, and operating temperature, circuit and process improve- ments of the orca series fpgas over time will result in significant improvement of the actual performance over those listed for a speed grade. even though lower speed grades may still be available, the distribution of yield to timing parameters may be several speed grades higher than that designated on a product brand. design practices need to consider best-case timing parameters (e.g., delays = 0), as well as worst-case timing. the routing delays are a function of fan-out and the capacitance associated with the cips and metal inter- connect in the path. the number of logic elements that can be driven (fan-out) by pfus is unlimited, although the delay to reach a valid logic level can exceed timing requirements. it is difficult to make accurate routing delay estimates prior to design compilation based on fan-out. this is because the cae software may delete redundant logic inserted by the designer to reduce fan- out, and/or it may also automatically reduce fan-out by net splitting. the waveform test points are given in the input/output buffer measurement conditions section of this data sheet. the timing parameters given in the electrical characteristics tables in this data sheet follow industry practices, and the values they reflect are described below. propagation delay the time between the specified reference points. the delays provided are the worst case of the tphh and tpll delays for noninverting func- tions, tplh and tphl for inverting functions, and tphz and tplz for 3-state enable. setup time the interval immediately preceding the transition of a clock or latch enable signal, during which the data must be stable to ensure it is recognized as the intended value. hold time the interval immediately following the transition of a clock or latch enable signal, during which the data must be held stable to ensure it is recognized as the intended value. 3-state enable the time from when a 3-state control signal becomes active and the output pad reaches the high-impedance state. pfu timing * four-input variables (k z [3:0]) path delays are valid for luts in both f4 (four-input lut) and f5 (five-input lut) modes. table 41. combinatorial pfu timin g characteristics or3cxx commercial: v dd = 5.0 v 5%, 0 c < t a < 70 c; industrial: v dd = 5.0 v 10%, C40 c < t a < +85 c. or3txxx commercial: v dd = 3.0 v to 3.6 v, 0 c < t a < 70 c; industrial: v dd = 3.0 v to 3.6 v, C40 c < t a < +85 c. parameter symbol speed unit -4 -5 -6 -7 min max min max min max min max combinatorial dela y s ( t j = +85 c, v dd = min ) : four-input variables ( kz [ 3:0 ] to f [ z ]) * five-input variables ( f5 [ a:d ] to f [ 0, 2, 4, 6 ]) two-level lut dela y ( kz [ 3:0 ] to f w/feedbk ) * two-level lut dela y ( f5 [ a:d ] to f w/feedbk ) three-level lut dela y ( kz [ 3:0 ] to f w/feedbk ) * three-level lut dela y ( f5 [ a:d ] to f w/feedbk ) c in to c out dela y ( lo g ic mode ) f4_del f5_del swl2_del swl2f5_del swl3_del swl3f5_del co_del 2.34 2.11 4.87 4.69 6.93 6.89 3.47 1.80 1.57 3.66 3.51 5.15 5.08 2.65 1.32 1.23 2.58 2.48 3.63 3.54 1.79 1.05 0.99 2.03 1.94 2.82 2.75 1.43 ns ns ns ns ns ns ns
lucent technologies inc. 105 data sheet june 1999 orca series 3c and 3t fpgas timing characteristics (continued) note: see table 46 for an explanation of fdbk_del and omux_del. 5-5751(f) figure 64. combinatorial pfu timing f4_del lut f4_del/ f5_del lut f5Cdel lut f4_del/ lut f4_del/ f5_del lut f4_del/ f5_del lut f4_del/ lut f4_del/ f5_del lut f4_del/ f5_del lut f4_del/ f5_del lut f4_del/ f5_del lut f4_del/ f5_del lut k z [3:0] k z [3:0], f5[a:d] k z [3:0] k z [3:0] f5[a:d] f5[a:d] f[7:0] f[6, 4, f[7:0] f[7:0] f[7:0] f[7:0] fdbkCdel o[9:0] swl2_del swl3_del swl2f5_del swl3f5_del pfu 8 4 omux_del 2, 0]
106 lucent technologies inc. data sheet june 1999 orca series 3c and 3t fpgas timing characteristics (continued) table 42. se q uential pfu timin g characteristics or3cxx commercial: v dd = 5.0 v 5%, 0 c < t a < 70 c; industrial: v dd = 5.0 v 10%, C40 c < t a < +85 c. or3txxx commercial: v dd = 3.0 v to 3.6 v, 0 c < t a < 70 c; industrial: v dd = 3.0 v to 3.6 v, C40 c < t a < +85 c . parameter symbol speed unit -4 -5 -6 -7 min max min max min max min max input requirements clock low time clkl_mpw 3.36 2.07 0.94 0.72 ns clock hi g h time clkh_mpw 1.61 1.06 0.54 0.45 ns global s/r pulse width ( gsrn ) gsr_mpw 3.36 2.07 0.94 0.72 ns local s/r pulse width lsr_mpw 3.36 2.07 0.94 0.72 ns combinatorial setup times ( t j = +85 c, v dd = min ) : four-input variables to clock ( kz [ 3:0 ] to clk ) * five-input variables to clock ( f5 [ a:d ] to clk ) data in to clock ( din [ 7:0 ] to clk ) carr y -in to clock, direct to regcout ( cin to clk ) clock enable to clock ( ce to clk ) clock enable to clock ( aswe to clk ) local set/reset to clock ( sync ) ( lsr to clk ) data select to clock ( sel to clk ) two-level lut to clock ( kz [ 3:0 ] to clk w/feedbk ) * two-level lut to clock ( f5 [ a:d ] to clk w/feedbk ) three-level lut to clock ( kz [ 3:0 ] to clk w/feedbk ) * three-level lut to clock ( f5 [ a:d ] to clk w/feedbk ) f4_set f5_set din_set cindir_set ce1_set ce2_set lsr_set sel_set swl2_set swl2f5_set swl3_set swl3f5_set 1.99 1.79 0.47 1.25 2.86 1.68 1.86 1.37 3.98 4.06 6.49 6.39 1.47 1.33 0.32 0.99 2.15 1.30 1.36 1.00 2.99 2.97 4.81 4.73 1.08 1.03 0.18 0.71 1.80 0.95 0.86 0.92 2.13 2.29 3.42 3.34 0.85 0.81 0.16 0.58 1.37 0.77 0.68 0.70 1.63 1.68 2.64 2.57 ns ns ns ns ns ns ns ns ns ns ns ns combinatorial hold times ( t j = all, v dd = all ) : data in ( din [ 7:0 ] from clk ) carr y -in from clock, direct to regcout ( cin from clk ) clock enable ( ce from clk ) clock enable from clock ( aswe from clk ) local set/reset from clock ( s y nc ) ( lsr from clk ) data select from clock ( sel from clk ) all others din_hld cindir_hld ce1_hld ce2_hld lsr_hld sel_hld 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 ns ns ns ns ns ns ns output characteristics se q uential dela y s ( t j = +85 c, v dd = min ) : local s/r ( as y nc ) to pfu out ( lsr to q [ 7:0 ] , reg- cout ) global s/r to pfu out ( gsrn to q [ 7:0 ] , regcout ) clock to pfu outre g ister ( clk to q [ 7:0 ] , reg- cout ) clock to pfu outlatch ( clk to q [ 7:0 ]) transparent latch ( din [ 7:0 ] to q [ 7:0 ]) lsr_del gsr_del reg_del ltch_del ltchd_del 7.02 5.21 2.38 2.51 2.73 5.29 3.90 1.75 1.88 2.10 3.64 2.55 1.26 1.21 1.38 2.90 2.00 0.97 0.96 1.12 ns ns ns ns ns * four-input variables ( k z [3:0] ) setup times are valid for luts in both f4 ( four-input lut ) and f5 ( five-input lut ) modes. note: the table shows worst-case dela y s. orca foundr y reports the dela y s for individual paths within a g roup of paths representin g the same timin g parameter and ma y accuratel y report dela y s that are less than those listed.
lucent technologies inc. 107 data sheet june 1999 orca series 3c and 3t fpgas timing characteristics (continued) table 43. ripple mode pfu timing characteristics or3cxx commercial: v dd = 5.0 v 5%, 0 c < t a < 70 c; industrial: v dd = 5.0 v 10%, C40 c < t a < +85 c. or3txxx commercial: v dd = 3.0 v to 3.6 v, 0 c < t a < 70 c; industrial: v dd = 3.0 v to 3.6 v, C40 c < t a < +85 c . parameter ( t j = +85 c, v dd = min ) symbol speed unit -4 -5 -6 -7 min max min max min max min max full ripple setup times ( b y te wide ) : operands to clock ( kz [ 1:0 ] to clk ) bitwise operands to clock ( kz [ 1:0 ] to clk at f [ z ]) fast carr y -in to clock ( fcin to clk ) carr y -in to clock ( cin to clk ) add/subtract to clock ( aswe to clk ) operands to clock ( kz [ 1:0 ] to clk at regcout ) fast carr y -in to clock ( fcin to clk at regcout ) carr y -in to clock ( cin to clk at regcout ) add/subtract to clock ( aswe to clk at regcout ) rip_set frip_set fcin_set cin_set as_set riprc_set fcinrc_set cinrc_set asrc_set 3.50 1.99 2.55 3.80 8.82 2.09 2.29 3.09 8.14 2.50 1.47 1.87 2.79 6.18 1.61 1.76 2.36 5.73 1.96 1.08 1.34 1.97 4.68 1.19 1.28 1.73 4.54 1.48 0.85 1.04 1.56 3.50 0.93 1.02 1.35 3.39 ns ns ns ns ns ns ns ns ns full ripple hold times ( t j = all, v dd = all ) : fast carr y -in from clock ( fcin from clk at reg- cout ) all others fcinrc_hld generic_hld 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 ns ns half ripple setup times ( nibble wide ) : operands to clock ( kz [ 1:0 ] to clk ) bitwise operands to clock ( kz [ 1:0 ] to clk at f [ z ]) fast carr y -in to clock ( fcin to clk ) carr y -in to clock ( cin to clk ) add/subtract to clock ( aswe to clk ) operands to clock ( kz [ 1:0 ] to clk at regcout ) fast carr y -in to clock ( fcin to clk at regcout ) carr y -in to clock ( cin to clk at regcout ) add/subtract to clock ( aswe to clk at regcout ) hrip_set hfrip_set hfcin_set hcin_set has_set hriprc_set hfcinrc_set hcinrc_set hasrc_set 3.91 1.99 2.55 3.80 8.82 3.03 2.29 3.09 8.14 2.81 1.47 1.87 2.79 6.18 2.31 1.76 2.36 5.73 2.21 1.08 1.34 1.97 4.68 1.68 1.28 1.73 4.54 1.66 0.85 1.04 1.56 3.50 1.32 1.02 1.35 3.39 ns ns ns ns ns ns ns ns ns half ripple hold times ( t j = all, v dd = all ) : fast carr y -in from clock ( hfcin from clk at reg- cout ) all others hfcinrc_hld generic_hld 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 ns ns note: the table shows worst-case dela y for the ripple chain. orca foundr y reports the dela y for individual paths within the ripple chain that will be less than or e q ual to those listed above.
108 lucent technologies inc. data sheet june 1999 orca series 3c and 3t fpgas timin g characteristics ( continued ) table 43. ri pp le mode pfu timin g characteristics (continued) or3cxx commercial: v dd = 5.0 v 5%, 0 c < t a < 70 c; industrial: v dd = 5.0 v 10%, C40 c < t a < +85 c. or3txxx commercial: v dd = 3.0 v to 3.6 v, 0 c < t a < 70 c; industrial: v dd = 3.0 v to 3.6 v, C40 c < t a < +85 c . parameter ( t j = +85 c, v dd = min ) symbol speed unit -4 -5 -6 -7 min max min max min max min max full ripple dela y s ( b y te wide ) : operands to carr y -out ( kz [ 1:0 ] to cout ) operands to carr y -out ( kz [ 1:0 ] to fcout ) operands to pfu out ( kz [ 1:0 ] to f [ 7:0 ]) bitwise operands to pfu out ( kz [ 1:0 ] to f [ z ]) fast carr y -in to carr y -out ( fcin to cout ) fast carr y -in to fast carr y -out ( fcin to fcout ) carr y -in to carr y -out ( cin to cout ) carr y -in to fast carr y -out ( cin to fcout ) fast carr y -in pfu out ( fcin to f [ 7:0 ]) carr y -in pfu out ( cin to f [ 7:0 ]) add/subtract to carr y -out ( aswe to cout ) add/subtract to carr y -out ( aswe to fcout ) add/subtract to pfu out ( aswe to f [ 7:0 ]) ripco_del ripfco_del rip_del frip_del fcinco_del fcinfco_del cinco_del cinfco_del fcin_del cin_del asco_del asfco_del as_del 5.32 5.30 7.37 2.34 2.59 2.57 3.47 3.46 6.03 6.91 8.28 8.11 10.66 4.11 4.10 5.60 1.80 1.99 1.98 2.65 2.64 4.55 5.21 5.89 5.78 7.55 2.98 2.98 4.18 1.32 1.43 1.41 1.79 1.78 3.21 3.53 4.58 4.48 5.85 2.32 2.32 3.10 1.05 1.14 1.13 1.43 1.43 2.51 3.05 3.45 3.38 4.38 ns ns ns ns ns ns ns ns ns ns ns ns ns half ripple dela y s ( nibble wide ) : operands to carr y -out ( kz [ 1:0 ] to cout ) operands to fast carr y -out ( kz [ 1:0 ] to fcout ) operands to pfu out ( kz [ 1:0 ] to f [ 3:0 ]) bitwise operands to pfu out ( kz [ 1:0 ] to f [ z ]) fast carr y -in to carr y -out ( fcin to cout ) fast carr y -in to fast carr y -out ( fcin to fcout ) carr y -in to carr y -out ( cin to cout ) carr y -in to carr y -out ( cin to fcout ) fast carr y -in pfu out ( fcin to f [ 3:0 ]) carr y -in pfu out ( cin to f [ 3:0 ]) add/subtract to carr y -out ( aswe to cout ) add/subtract to carr y -out ( aswe to fcout ) add/subtract to pfu out ( aswe to f [ 3:0 ]) hripco_del hripfco_del hrip_del hfrip_del hfcinco_del hfcinfco_del hcinco_del hcinfco_del hfcin_del hcin_del hasco_del hasfco_del has_del 5.32 5.30 5.50 2.34 2.59 2.57 3.47 3.46 3.76 4.65 8.28 8.11 9.12 4.11 4.10 4.07 1.80 1.99 1.98 2.65 2.64 2.84 3.50 5.89 5.78 6.49 2.98 2.98 3.20 1.32 1.43 1.41 1.79 1.78 2.01 2.33 4.58 4.48 4.86 2.32 2.32 2.40 1.05 1.14 1.13 1.43 1.43 1.58 2.12 3.45 3.38 3.69 ns ns ns ns ns ns ns ns ns ns ns ns ns note: the table shows worst-case dela y for the ripple chain. orca foundr y reports the dela y for individual paths within the ripple chain that will be less than or e q ual to those listed above.
lucent technologies inc. 109 data sheet june 1999 orca series 3c and 3t fpgas timing characteristics (continued) table 44. synchronous memory write characteristics or3cxx commercial: v dd = 5.0 v 5%, 0 c < t a < 70 c; industrial: v dd = 5.0 v 10%, C40 c < t a < +85 c. or3txxx commercial: v dd = 3.0 v to 3.6 v, 0 c < t a < 70 c; industrial: v dd = 3.0 v to 3.6 v, C40 c < t a < +85 c. * the ram is written on the inactive clock ed g e followin g the active ed g e that latches the address, data, and control si g nals. note: the table shows worst-case dela y s. orca foundr y reports the dela y s for individual paths within a g roup of paths representin g the same timin g parameter and ma y accuratel y report dela y s that are less than those listed. 5-4621(f) figure 65. s y nchronous memor y write characteristics parameter symbol speed unit -4 -5 -6 -7 min max min max min max min max write operation for ram mode: maximum frequenc y clock low time clock hi g h time clock to data valid (clk to f[6, 4, 2, 0])* smclk_frq smclkl_mpw smclkh_mpw mem_del 2.34 3.79 151.00 10.00 1.80 2.77 197.00 7.14 1.32 2.13 254.00 5.00 1.05 1.62 315.00 4.08 mhz ns ns ns write operation setup time: address to clock (cin to clk) address to clock (din[7, 5, 3, 1] to clk) data to clock (din[6, 4, 2, 0] to clk) write enable (wren) to clock (aswe to clk) write-port enable 0 (wpe0) to clock (ce to clk) write-port enable 1 (wpe1) to clock (lsr to clk) wa4_set wa_set wd_set we_set wpe0_set wpe1_set 1.25 0.72 0.02 0.18 2.25 2.79 0.99 0.52 0.06 0.16 1.69 2.13 0.71 0.35 0.00 0.14 1.16 1.58 0.58 0.28 0.00 0.12 0.84 1.31 ns ns ns ns ns ns write operation hold time: address from clock (cin from clk) address from clock (din[7, 5, 3, 1] from clk) data from clock (din[6, 4, 2, 0] from clk) write enable (wren) from clock (aswe from clk) write-port enable 0 (wpe0) from clock (ce from clk) write-port enable 1 (wpe1) from clock (lsr from clk) wa4_hld wa_hld wd_hld we_hld wpe0_hld wpe1_hld 0.00 0.00 0.59 0.03 0.00 0.00 0.00 0.00 0.42 0.00 0.00 0.00 0.00 0.00 0.40 0.08 0.00 0.00 0.00 0.00 0.32 0.06 0.00 0.00 ns ns ns ns ns ns ck f[6, 4, 2, 0] cin, din[7, 5, 3, 1] din[6, 4, 2, 0] mem_del wa4_set aswe (wren) ce (wpe0), t sch t scl wa4_hld wd_set wd_hld we_set we_hld wpe0_set wpe0_hld wa_set wa_hld wpe1_set wpe1_hld lsr (wpe1)
110 lucent technologies inc. data sheet june 1999 orca series 3c and 3t fpgas timing characteristics (continued) table 45. s y nchronous memor y read characteristics or3cxx commercial: v dd = 5.0 v 5%, 0 c < t a < 70 c; industrial: v dd = 5.0 v 10%, C40 c < t a < +85 c. or3txxx commercial: v dd = 3.0 v to 3.6 v, 0 c < t a < 70 c; industrial: v dd = 3.0 v to 3.6 v, C40 c < t a < +85 c. note: the table shows worst-case dela y s. orca foundr y reports the dela y s for individual paths within a g roup of paths representin g the same timin g parameter and ma y accuratel y report dela y s that are less than those listed. 5-4622(f) figure 66. synchronous memory read cycle parameter ( t j = 85 c, v dd = min ) symbol speed unit -4 -5 -6 -7 min max min max min max min max read operation: data valid after address ( kz [ 3:0 ] to f [ 6, 4, 2, 0 ]) data valid after address ( f5 [ a:d ] to f [ 6, 4, 2, 0 ]) ra_del ra4_del 2.34 2.11 1.80 1.57 1.32 1.23 1.05 0.99 ns ns read operation, clockin g data into latch/ff: address to clock setup time ( kz [ 3:0 ] to clk ) address to clock setup time ( f5 [ a:d ] to clk ) address from clock hold time ( kz [ 3:0 ] from clk ) address from clock hold time ( f5 [ a:d ] from clk ) clock to pfu outputre g ister ( clk to q [ 6, 4, 2, 0 ]) read c y cle dela y ra_set ra4_set ra_hld ra4_hld reg_del smrd_cyc 1.99 1.79 0.00 0.00 2.38 10.48 1.47 1.33 0.00 0.00 1.75 7.66 1.08 1.03 0.00 0.00 1.26 7.53 0.85 0.81 0.00 0.00 0.97 5.78 ns ns ns ns ns ns kz[3:0], f5[a:d] f[6, 4, 2, 0] clk q[3:0] ra_del ra4_del ra_set ra4_set reg_del ra_hld ra4_hld smrd_cyc
lucent technologies inc. 111 data sheet june 1999 orca series 3c and 3t fpgas timing characteristics (continued) plc timing table 46 . pfu out p ut mux and direct routin g timin g characteristics or3cxx commercial: v dd = 5.0 v 5%, 0 c < t a < 70 c; industrial: v dd = 5.0 v 10%, C40 c < t a < +85 c. or3txxx commercial: v dd = 3.0 v to 3.6 v, 0 c < t a < 70 c; industrial: v dd = 3.0 v to 3.6 v, C40 c < t a < +85 c. * this is g eneral feedback usin g switchin g se g ments. see the combinatorial pfu timin g table for softwired look-up table feedback timin g . slic timing table 47 . su pp lemental lo g ic and interconnect cell ( slic ) timin g characteristics or3cxx commercial: v dd = 5.0 v 5%, 0 c < t a < 70 c; industrial: v dd = 5.0 v 10%, C40 c < t a < +85 c. or3txxx commercial: v dd = 3.0 v to 3.6 v, 0 c < t a < 70 c; industrial: v dd = 3.0 v to 3.6 v, C40 c < t a < +85 c. parameter ( t j = 85 c, v dd = min ) symbol speed unit -4 -5 -6 -7 min max min max min max min max pfu output mux ( fan-out = 1 ) output mux dela y ( f [ 7:0 ] /q [ 7:0 ] to o [ 9:0 ]) carr y -out mux dela y ( cout to o9 ) re g istered carr y -out mux dela y ( regcout to o8 ) omux_del coo9_del rcoo8_del 0.50 0.34 0.34 0.39 0.26 0.26 0.35 0.24 0.24 0.28 0.18 0.18 ns ns ns direct routing pfu feedback ( xsw ) * pfu to ortho g onal pfu dela y ( xsw to xsw ) pfu to dia g onal pfu dela y ( xbid to xsw ) fdbk_del odir_del ddir_del 1.74 2.21 2.69 1.41 1.77 2.19 1.48 1.75 2.53 1.14 1.39 1.98 ns ns ns parameter ( t j = 85 c, v dd = min ) symbol speed unit -4 -5 -6 -7 min max min max min max min max 3-statable bidis bidi dela y ( brx to blx, blx to brx ) bidi dela y ( ox to brx, ox to blx ) bidi 3-state enable/disable dela y ( tri to bl, br ) bidi 3-state enable/disable dela y ( bl, br via dec, tri to bl, br ) buf_del obuf_del tri_del dectri_del 0.84 0.72 2.55 3.59 0.70 0.61 1.90 2.65 0.94 0.87 1.31 1.91 0.77 0.70 1.01 1.48 ns ns ns ns decoder decoder dela y ( br [ 9:8 ] , bl [ 9:8 ] to dec ) decoder dela y ( br [ 7:0 ] , bl [ 7:0 ] to dec ) dec98_del dec_del 2.39 2.35 1.85 1.82 1.27 1.23 1.02 0.99 ns ns
112 lucent technologies inc. data sheet june 1999 orca series 3c and 3t fpgas timing characteristics (continued) pio timing table 48. pro g rammable i/o ( pio ) timin g characteristics or3cxx commercial: v dd = 5.0 v 5%, 0 c < t a < 70 c; industrial: v dd = 5.0 v 10%, C40 c < t a < +85 c. or3txxx commercial: v dd = 3.0 v to 3.6 v, 0 c < t a < 70 c; industrial: v dd = 3.0 v to 3.6 v, C40 c < t a < +85 c. parameter symbol speed unit -4 -5 -6 -7 min max min max min max min max input delays ( t j = 85 c, v dd = min ) input rise time in_ris 500 500 500 500 ns input fall time in_fal 500 500 500 500 ns pio direct delays: pad to in (pad to clk in) pad to in (pad to in1, in2) pad to in delayed (pad to in1, in2) ckin_del in_del ind_del 1.41 2.16 9.05 1.26 1.87 7.83 0.64 1.28 6.64 0.41 0.90 7.27 ns ns ns pio transparent latch delays: pad to in (pad to in1, in2) pad to in delayed (pad to in1, in2) latch_del latchd_del 4.11 10.58 3.25 9.05 2.52 7.67 1.82 7.65 ns ns input latch/ff setup timing: pad to expressclk (fast-capture latch/ff) pad delayed to expressclk (fast-capture latch/ff) pad to clock (input latch/ff) pad delayed to clock (input latch/ff) clock enable to clock (ce to clk) local set/reset (sync) to clock (lsr to clk) inrege_set inreged_set inreg_set inregd_set ince_set inlsr_set 5.93 12.86 1.62 8.57 2.03 1.79 4.82 11.03 1.42 7.36 1.64 1.45 3.63 9.18 0.71 5.91 1.29 1.14 3.23 9.68 0.50 7.06 1.00 0.89 ns ns ns ns ns ns input ff/latch hold timing: pad from expressclk (fast-capture latch/ff) pad delayed from expressclk (fast-capture latch/ff) pad from clock (input latch/ff) pad delayed from clock (input latch/ff) clock enable from clock (ce from clk) local set/reset (sync) from clock (lsr from clk) inrege_hld inreged_hld inreg_hld inregd_hld ince_hld inlsr_hld 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 ns ns ns ns ns ns clock-to-in delay (ff clk to in1, in2) clock-to-in delay (latch clk to in1, in2) local s/r (async) to in (lsr to in1, in2) local s/r (async) to in (lsr to in1, in2) latchff in latch mode global s/r to in (gsrn to in1, in2) inreg_del inltch_del inlsr_del inlsrl_del ingsr_del 4.05 4.08 6.11 5.89 5.38 3.14 3.19 4.76 4.66 4.22 2.53 2.62 3.81 3.57 3.44 2.05 2.14 3.17 2.98 2.88 ns ns ns ns ns note: the dela y s for all input buffers assume an input rise/fall time of < 1 v/ns.
lucent technologies inc. 113 data sheet june 1999 orca series 3c and 3t fpgas timing characteristics (continued) table 48 . pro g rammable i/o ( pio ) timin g characteristics (continued) or3cxx commercial: v dd = 5.0 v 5%, 0 c < t a < 70 c; industrial: v dd = 5.0 v 10%, C40 c < t a < +85 c. or3txxx commercial: v dd = 3.0 v to 3.6 v, 0 c < t a < 70 c; industrial: v dd = 3.0 v to 3.6 v, C40 c < t a < +85 c. parameter symbol speed unit -4 -5 -6 -7 min max min max min max min max output delays ( t j = 85 c, v dd = min, c l = 50 pf ) output to pad ( out2, out1 direct to pad ) : fast slewlim sinklim outf_del outsl_del outsi_del 5.09 7.86 9.41 4.21 6.49 7.98 2.63 3.49 8.08 2.17 2.91 7.32 ns ns ns 3-state enable/disable dela y ( ts to pad ) : fast slewlim sinklim tsf_del tssl_del tssi_del 4.93 7.70 9.25 4.09 6.37 7.86 2.33 3.00 7.95 1.88 2.41 7.23 ns ns ns local set/reset ( as y nc ) to pad ( lsr to pad ) : fast slewlim sinklim outlsrf_del outlsrsl_del outlsrsi_del 9.03 11.79 13.35 7.25 9.53 11.02 4.96 5.82 10.38 3.94 4.67 9.10 ns ns ns global set/reset to pad ( gsrn to pad ) : fast slewlim sinklim outgsrf_del outgsrsl_del outgsrsi_del 8.30 11.06 12.62 6.69 8.97 10.46 4.39 5.07 10.02 3.46 3.99 8.81 ns ns ns output ff setup timin g : out to expressclk ( out [ 2:1 ] to eclk ) out to clock ( out [ 2:1 ] to clk ) clock enable to clock ( ce to clk ) local set/reset ( s y nc ) to clock ( lsr to clk ) oute_set out_set outce_set outlsr_set 0.00 0.00 0.91 0.41 0.00 0.00 0.67 0.32 0.00 0.00 0.56 0.26 0.00 0.00 0.45 0.24 ns ns ns ns output ff hold timin g : out from expressclk ( out [ 2:1 ] from eclk ) out from clock ( out [ 2:1 ] from clk ) clock enable from clock ( ce from clk ) local set/reset ( s y nc ) from clock ( lsr from clk ) oute_hld out_hld outce_hld outlsr_hld 0.73 0.73 0.00 0.00 0.58 0.58 0.00 0.00 0.36 0.36 0.00 0.00 0.29 0.29 0.00 0.00 ns ns ns ns clock to pad dela y ( eclk, sclk to pad ) : fast slewlim sinklim outregf_del outregsl_del outregsi_del 6.71 9.47 11.03 5.44 7.71 9.20 3.56 4.42 8.98 2.78 3.52 7.94 ns ns ns additional dela y if usin g open drain od_del 0.20 0.16 0.10 0.08 ns note: the dela y s for all input buffers assume an input rise/fall time of < 1 v/ns.
114 lucent technologies inc. data sheet june 1999 orca series 3c and 3t fpgas timing characteristics (continued) table 48. pro g rammable i/o ( pio ) timin g characteristics (continued) or3cxx commercial: v dd = 5.0 v 5%, 0 c < t a < 70 c; industrial: v dd = 5.0 v 10%, C40 c < t a < +85 c. or3txxx commercial: v dd = 3.0 v to 3.6 v, 0 c < t a < 70 c; industrial: v dd = 3.0 v to 3.6 v, C40 c < t a < +85 c. parameter symbol speed unit -4 -5 -6 -7 min max min max min max min max pio logic block delays out to pad ( out [ 2:1 ] via lo g ic to pad ) : fast slewlim sinklim outlf_del outlsl_del outlsi_del 5.09 7.86 9.41 4.21 6.49 7.98 2.63 3.49 8.08 2.17 2.91 7.32 ns ns ns outre g to pad ( outreg via lo g ic to pad ) : fast slewlim sinklim outrf_del outrsl_del outrsi_del 6.71 9.47 11.03 5.44 7.71 9.20 3.56 4.42 8.98 2.78 3.52 7.94 ns ns ns clock to pad ( eclk, clk via lo g ic to pad ) : fast slewlim sinklim outcf_del outcsl_del outcsi_del 6.97 9.74 11.29 5.68 7.96 9.45 3.71 4.57 9.13 2.91 3.64 8.07 ns ns ns 3-state ff delays 3-state enable/disable dela y ( ts direct to pad ) : fast slewlim sinklim tsf_del tssl_del tssi_del 4.93 7.70 9.25 4.09 6.37 7.86 2.33 3.00 7.95 1.88 2.41 7.23 ns ns ns local set/reset ( as y nc ) to pad ( lsr to pad ) : fast slewlim sinklim tslsrf_del tslsrsl_del tslsrsi_del 8.25 11.01 12.57 6.65 8.92 10.41 4.24 4.92 9.87 3.39 3.92 8.74 ns ns ns global set/reset to pad ( gsrn to pad ) : fast slewlim sinklim tsgsrf_del tsgsrsl_del tsgsrsi_del 7.52 10.28 11.84 6.09 8.36 9.85 3.88 4.55 9.51 3.11 3.64 8.45 ns ns ns 3-state ff setup timin g : ts to expressclk ( ts to eclk ) ts to clock ( ts to clk ) local set/reset ( s y nc ) to clock ( lsr to clk ) tse_set ts_set tslsr_set 0.00 0.00 0.28 0.00 0.00 0.21 0.00 0.00 0.17 0.00 0.00 0.18 ns ns ns 3-state ff hold timin g : ts from expressclk ( ts from eclk ) ts from clock ( ts from clk ) local set/reset ( s y nc ) from clock ( lsr from clk ) tse_hld ts_hld tslsr_hld 0.85 0.85 0.00 0.68 0.68 0.00 0.44 0.44 0.00 0.34 0.34 0.00 ns ns ns clock to pad dela y ( eclk, sclk to pad ) : fast slewlim sinklim tsregf_del tsregsl_del tsregsi_del 5.94 8.70 10.26 4.82 7.10 8.59 2.84 3.52 8.47 2.23 2.76 7.58 ns ns ns note: the dela y s for all input buffers assume an input rise/fall time of < 1 v/ns.
lucent technologies inc. 115 data sheet june 1999 orca series 3c and 3t fpgas timing characteristics (continued) special function blocks timing table 49. microprocessor interface (mp i) timing characteristics or3cxx commercial: v dd = 5.0 v 5%, 0 c < t a < 70 c; industrial: v dd = 5.0 v 10%, C40 c < t a < +85 c. or3txxx commercial: v dd = 3.0 v to 3.6 v, 0 c < t a < 70 c; industrial: v dd = 3.0 v to 3.6 v, C40 c < t a < +85 c. 1. for user s y stem flexibilit y , cs0 and cs1 ma y be set up to an y one of the three risin g clock ed g es, be g innin g with the risin g clock ed g e when mpi_strb is low. if both chip selects are valid and the setup time is met, the mpi will latch the chip select state, and cs0 and cs1 ma y g o inactive before the end of the read/write c y cle. 2. 0.5 mpi_clk. 3. write data and w/r have to be valid startin g from the clock c y cle after both ads and cs0 and cs1 are reco g nized. 4. write data and w/r have to be held until the microprocessor receives a valid rdyrcv . notes: read and write descriptions are referenced to the host microprocessor; e. g ., a read is a read b y the host ( powerpc , i960 ) from the fpga. powerpc and i960 timin g s to/from the clock are relative to the clock at the fpga microprocessor interface clock pin ( mpi_clk ) . parameter symbol speed unit C4 C5 C6 C7 minmaxminmaxminmaxminmax powerpc interface timing ( t j = 85 c, v dd = min ) transfer acknowled g e dela y ( clk to ta ) burst inhibit dela y ( clk to bin ) transfer acknowled g e dela y to hi g h impedance burst inhibit dela y to hi g h impedance write data setup time ( data to ts ) write data hold time ( data from clk while mpi_ack low ) address setup time ( addr to ts ) address hold time ( addr from clk while mpi_ack low ) read/write setup time ( r/w to ts ) read/write hold time ( r/w from clk while mpi_ack low ) chip select setup time ( cs0 , cs1 to ts ) chip select hold time ( cs0 , cs1 from clk ) user address dela y ( pad to ua [ 3:0 ]) user read/write dela y ( pad to urdwr_del ) ta_del bi_del ta_delz bi_delz wd_set wd_hld a_set a_hld rw_set rw_hld cs_set cs_hld ua_del urdwr_del 0.0 0.0 0.0 0.0 0.0 0.0 0.3 0.0 11.6 11.6 ( 2 ) ( 2 ) 3.3 7.0 0.0 0.0 0.0 0.0 0.0 0.0 .25 0.0 9.3 9.3 ( 2 ) ( 2 ) 2.6 5.4 0.0 0.0 0.0 0.0 0.0 0.0 .14 0.0 8.0 8.0 ( 2 ) ( 2 ) 2.3 4.2 0.0 0.0 0.0 0.0 0.0 0.0 .12 0.0 6.8 6.8 ( 2 ) ( 2 ) 1.9 3.6 ns ns ns ns ns ns ns ns ns ns ns ns ns ns i960 interface timing ( t j = 85 c, v dd = min ) addr/data select to ale ( ads , to ale low ) addr/data select to ale ( ads , from ale low ) read y /receive dela y ( clk to rdyrcv ) read y /receive dela y to hi g h impedance write data setup time write data hold time address setup time ( addr to ale low ) address hold time ( addr from ale low ) b y te enable setup time ( be0 , be1 to ale low ) b y te enable hold time ( be0 , be1 from ale low ) read/write setup time read/write hold time chip select setup time ( cs0 , cs1 to clk ) ( 1 ) chip select hold time ( cs0 , cs1 from clk ) ( 1 ) user address dela y ( clk low to ua [ 3:0 ]) user read/write dela y ( pad to urdwr_del ) adsn_set adsn_hld rdyrcv_del rdyrcv_delz wd_set wd_hld a_set a_hld be_set be_hld rw_set rw_hld cs_set cs_hld ua_del urdwr_del 2.0 0.0 ( 3 ) ( 4 ) 2.0 2.0 2.0 2.0 ( 3 ) ( 4 ) 2.0 0.0 11.6 ( 2 ) 6.6 7.0 1.8 0.0 ( 3 ) ( 4 ) 1.8 1.8 1.8 1.8 ( 3 ) ( 4 ) 1.8 0.0 9.3 ( 2 ) 4.3 5.4 1.6 0.0 ( 3 ) ( 4 ) 0.50 0.51 0.50 0.51 ( 3 ) ( 4 ) 0.45 0.0 8.0 ( 2 ) 4.1 4.2 1.4 0.0 ( 3 ) ( 4 ) ( 3 ) ( 4 ) 0.0 6.8 ( 2 ) 0.42 0.44 0.42 0.44 0.38 3.5 3.6 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
116 lucent technologies inc. data sheet june 1999 orca series 3c and 3t fpgas timin g characteristics ( continued ) table 49. microprocessor interface (mp i) timing characteristics (continued) or3cxx commercial: v dd = 5.0 v 5%, 0 c < t a < 70 c; industrial: v dd = 5.0 v 10%, C40 c < t a < +85 c. or3txxx commercial: v dd = 3.0 v to 3.6 v, 0 c < t a < 70 c; industrial: v dd = 3.0 v to 3.6 v, C40 c < t a < +85 c. 1. for user s y stem flexibilit y , cs0 and cs1 ma y be set up to an y one of the three risin g clock ed g es, be g innin g with the risin g clock ed g e when mpi_strb is low. if both chip selects are valid and the setup time is met, the mpi will latch the chip select state, and cs0 and cs1 ma y g o inactive before the end of the read/write c y cle. 2. 0.5 mpi_clk. 3. write data and w/r have to be valid startin g from the clock c y cle after both ads and cs0 and cs1 are reco g nized. 4. write data and w/r have to be held until the microprocessor receives a valid rdyrcv . 5. user lo g ic dela y has no predefined value. the user must g enerate a uend si g nal to complete the c y cle. 6. ustart_del is based on the fallin g clock ed g e. 7. there is no specific time associated with this delay. the user must assert uend low to complete this cycle. 8. the user must assert interrupt request low until a service routine is executed. 9. this should be at least one mpi_clk c y cle. 10. user should set up read data so that rds_set and rds_hld can be met for the microprocessor timing. notes: read and write descriptions are referenced to the host microprocessor; e. g ., a read is a read b y the host ( powerpc , i960 ) from the fpga. powerpc and i960 timin g s to/from the clock are relative to the clock at the fpga microprocessor interface clock pin ( mpi_clk ) . parameter symbol speed unit C4 C5 C6 C7 min max min max min max min max user lo g ic dela y ( 5 ) user lo g ic dela y ns user start dela y ( mpi_clk fallin g to ustart ) ( 6 ) ustart_del 3.6 3.4 3.3 2.8 ns user start clear dela y ( mpi_clk to ustart ) ustartclr_del 7.5 7.3 7.1 6.0 ns user end delay (ustart low to uend low) ( 7 ) uend_del ns s y nchronous user timin g : user end setup ( uend to mpi_clk ) uend_set 0.00 0.00 0.00 0.00 ns user end hold ( uend to mpi_clk ) uend_hld 1.0 0.95 0.88 0.75 ns data setup for read ( d [ 7:0 ] to mpi_clk ) ( 9 ) rds_set ns data hold for read ( d [ 7:0 ] from mpi_clk ) ( 9 ) rds_hld ns as y nchronous user timin g : user end to read data dela y ( uend to d [ 7:0 ] ) ( 10 ) rda_del ns data hold from user start ( low ) ( 9 ) rda_hld ns interrupt re q uest pulse width ( 8 ) tuirq_pw ns
lucent technologies inc. 117 data sheet june 1999 orca series 3c and 3t fpgas timing characteristics (continued) 5-5832(f) figure 67. mpi powerpc user space read timing 5-5840(f) figure 68. mpi powerpc user space write timing mpi_clk a[4:0] mpi_rw (rd/wr ) cs0 , cs1 d[7:0] mpi_strb (ts ) ua[3:0] urdwrn ustart uend mpi_ack (ta ) mpi_bi (bi ) a_set rw_set cs_set urdwr_del rds_set a_hld cs_hld rds_hld rda_del rda_hld ustart_del user logic delay ta_del bi_del bi_del ta_del uend_del ustartclr_del rw_hld ua_del uend_set ta_delz bi_delz mpi_clk a[4:0] mpi_rw (rd/wr ) cs0 , cs1 d[7:0] mpi_strb (ts ) ua[3:0] urdwrn ustart uend mpi_ack (ta ) mpi_bi (bi ) a_set rw_set cs_set urdwr_del uend_set a_hld rw_hld cs_hld wd_hld ustart_del user logic delay ta_del bi_del bi_del ta_del uend_del ustartclr_del ua_del bi_delz ta_delz wd_set
118 lucent technologies inc. data sheet june 1999 orca series 3c and 3t fpgas timing characteristics (continued) 5-5832(f).c figure 69. mpi powerpc internal read timin g 5-5840(f).e figure 70. mpi powerpc internal write timin g mpi_clk a[4:0] mpi_rw (rd/wr ) cs0 , cs1 d[7:0] mpi_strb (ts ) ua[3:0] urdwrn mpi_ack (ta ) mpi_bi (bi ) a_set rw_set cs_set urdwr_del rds_set a_hld cs_hld rds_hld rda_del rda_hld ta_del bi_del bi_del ta_del rw_hld ua_del uend_set ta_delz bi_delz mpi_clk a[4:0] mpi_rw (rd/wr ) cs0 , cs1 d[7:0] mpi_strb (ts ) ua[3:0] urdwrn mpi_ack (ta ) mpi_bi (bi ) a_set rw_set cs_set urdwr_del a_hld rw_hld cs_hld wd_hld ta_del bi_del bi_del ta_del ua_del bi_delz ta_delz wd_set
lucent technologies inc. 119 data sheet june 1999 orca series 3c and 3t fpgas timing characteristics (continued) 5-5831(f).b figure 71. mpi i960 user s p ace read timing 5-5830(f).b figure 72. mpi i960 user s p ace write timin g mpi_clk d[7:0] mpi_rw (w/r ) cs0 , cs1 mpi_ale (ale) mpi_strb (ads ) ua[3:0] urdwrn ustart uend mpi_ack (rdyrcv ) adsn_hld a_set addr data ua_del uend_set rdyrcv_del ustart_del user logic delay rdyrcv_del uend_del ustartclr_del cs_hld rds_hld rw_hld rds_set rda_del rda_hld be0 , be1 be_hld be_set rdyrcv_delz urdwr_del adsn_set rw_set a_hld cs_set mpi_clk d[7:0] mpi_rw (w/r ) cs0 , cs1 mpi_ale (ale) mpi_strb (ads ) ua[3:0] urdwrn ustart uend mpi_ack (rdyrcv ) a_hld adsn_hld a_set data urdwr_del uend_set rdyrcv_del ustart_del user logic delay rdyrcv_del uend_del ustartclr_del cs_hld wd_hld rw_hld wd_set ua_del rdyrcv_delz addr cs_set rw_set adsn_set
120 lucent technologies inc. data sheet june 1999 orca series 3c and 3t fpgas timing characteristics (continued) 5-5831(f).c figure 73. mpi i960 internal read timing 5-5830(f).c figure 74. mpi i960 internal write timin g mpi_clk d[7:0] mpi_rw (w/r ) cs0 , cs1 mpi_ale (ale) mpi_strb (ads ) ua[3:0] urdwrn mpi_ack (rdyrcv ) adsn_hld a_set addr data ua_del rdyrcv_del rdyrcv_del cs_hld rds_hld rw_hld rds_set rda_del rda_hld be0 , be1 be_hld be_set rdyrcv_delz urdwr_del adsn_set rw_set a_hld cs_set mpi_clk d[7:0] mpi_rw (w/r ) cs0 , cs1 mpi_ale (ale) mpi_strb (ads ) ua[3:0] urdwrn mpi_ack (rdyrcv ) a_hld adsn_hld a_set data urdwr_del rdyrcv_del rdyrcv_del cs_hld wd_hld rw_hld wd_set ua_del rdyrcv_delz addr cs_set rw_set adsn_set
lucent technologies inc. 121 data sheet june 1999 orca series 3c and 3t fpgas timing characteristics (continued) table 50. programmable clock manager ( pcm ) timing characteristics (preliminary information) or3cxx commercial: v dd = 5.0 v 5%, 0 c t a < 70 c; industrial: v dd = 5.0 v 10%, C40 c < t a < +85 c. or3txxx commercial: v dd = 3.0 v to 3.6 v, 0 c < t a < 70 c; industrial: v dd = 3.0 v to 3.6 v, C40 c < t a < +85 c. * input frequency tolerance is the allowed input clock frequency change in parts per million. ? see table 29 and table 30 for acquisition times for individual frequencies. ? pll mode, divider reg = 1111111 (input freq. = output freq.). note: all timing values for the pcm are preliminary information. parameter symbol speed unit -4 -5 -6 -7 minmaxminmaxminmaxminmax input clock frequency: fpcmi or3cxx 51335133 mhz or3txxx 5 133 5 133 5 133 mhz output clock frequency: fpcmo or3cxx 51355135 mhz or3txxx 5 100 5 100 5 100 mhz input clock duty cycle pcmi_duty 30.00 70.00 30.00 70.00 30.00 70.00 30.00 70.00 % output clock duty cycle pcmo_duty 3.13 96.90 3.13 96.90 3.13 96.90 3.13 96.90 % input frequency tolerance* ftol 26400 26400 26400 26400 ppm pcm acquisition time (clk in to lock) pcm_acq ? 36 100 36 100 36 100 36 100 s pcm off delay (config. done-l, we to pcm power off) pcmoff_del 100.0 100.0 100.0 100.0 ns pcm delay in dll mode (propagation delay) pcmdll-del 1.95 1.82 1.63 1.50 ns pcm delay in pll mode (propagation delay) pcmpll_del 0.00 0.00 0.00 0.00 ns pcm clock in to pcm clock out (clk in to eclk) ? pcmbye_del 0.47 0.36 0.26 0.24 ns pcm clock in to pcm clock out (clk in to sclk) ? pcmbys_del 0.47 0.36 0.26 0.24 ns routed clock-in delay (routing to pcm phase detect, using div0) rtckd_del 1.30 1.10 0.90 tbd ns system clock-out delay (pcm oscilla- tor to sclk output at pcm) pcmsck_del 2.70 2.20 1.90 tbd ns parameter symbol f out (mhz) pll mode dll mode unit output jitter outjit 520 250 200 ps 2130 210 170 ps 3140 180 145 ps 4150 155 123 ps 5160 130 105 ps 6170 110 90 ps 7180 95 75 ps 8190 80 65 ps 91100 70 55 ps
122 lucent technologies inc. data sheet june 1999 orca series 3c and 3t fpgas timing characteristics (continued) table 51. boundary-scan timing characteristics or3cxx commercial: v dd = 5.0 v 5%, 0 c < t a < 70 c; industrial: v dd = 5.0 v 10%, C40 c < t a < +85 c. or3txxx commercial: v dd = 3.0 v to 3.6 v, 0 c < t a < 70 c; industrial: v dd = 3.0 v to 3.6 v, C40 c < t a < +85 c. 5-6764(f) figure 75. boundary-scan timing diagram parameter s y mbol min max unit tdi/tms to tck setup time t s 25.0 ns tdi/tms hold time from tck t h 0.0 ns tck low time t cl 50.0 ns tck hi g h time t ch 50.0 ns tck to tdo dela y t d 20.0 ns tck fre q uenc y t tck 10.0 mhz tck tms tdi tdo t s t h t d
lucent technologies inc. 123 data sheet june 1999 orca series 3c and 3t fpgas timing characteristics (continued) clock timing table 52 . expressclk ( eclk ) and fast clock ( fclk ) timin g characteristics or3cxx commercial: v dd = 5.0 v 5%, 0 c < t a < 70 c; industrial: v dd = 5.0 v 10%, C40 c < t a < +85 c. or3txxx commercial: v dd = 3.0 v to 3.6 v, 0 c < t a < 70 c; industrial: v dd = 3.0 v to 3.6 v, C40 c < t a < +85 c. notes: the eclk dela y s are to all of the pics on one side of the device for middle pin input, or two sides of the device for corner pin input. the d ela y includes both the input buffer dela y and the clock routin g to the pic clock input. the fclk dela y s are for a full y routed clock tree that uses the expressclk input into the fast clock network. it includes both the input buffer dela y and the clock routin g to the pfu clk input. the dela y will be reduced if an y of the clock branches are not used. device ( t j = 85 c, v dd = min ) symbol speed unit -4 -5 -6 -7 min max min max min max min max clock control timin g dela y throu g h clkcntrl ( input from corner ) eclkc_del 0.31 0.31 0.31 0.31 ns dela y throu g h clkcntrl ( input from inter- nal clock controller pad ) eclkm_del 1.54 1.17 1.00 0.92 ns clock shutoff timin g : setup from middle eclk ( shut off to clk ) hold from middle eclk ( shut off from clk ) setup from corner eclk ( shut off to clk ) hold from corner eclk ( shut off from clk ) offm_set offm_hld offc_set offc_hld 0.77 0.00 0.77 0.00 0.51 0.00 0.51 0.00 0.44 0.00 0.44 0.00 0.41 0.00 0.41 0.00 ns ns ns ns eclk dela y ( middle pad ) : or3t20 or3t30 or3c/t55 or3c/t80 or3t125 eclkm_del 3.50 3.67 2.56 2.62 2.74 2.86 3.06 2.05 2.08 2.13 2.19 2.29 1.78 1.80 1.85 1.90 1.98 ns ns ns ns ns eclk dela y ( corner pad ) : or3t20 or3t30 or3c/t55 or3c/t80 or3t125 eclkc_del 5.47 5.64 4.48 4.53 4.64 4.77 4.96 3.85 3.97 4.22 4.47 4.85 3.36 3.47 3.69 3.92 4.27 ns ns ns ns ns fclk dela y ( middle pad ) : or3t20 or3t30 or3c/t55 or3c/t80 or3t125 fclkm_del 8.24 8.87 5.91 6.12 6.59 7.11 7.98 4.59 4.66 4.83 5.01 5.33 3.81 3.89 4.06 4.26 4.59 ns ns ns ns ns fclk dela y ( corner pad ) : or3t20 or3t30 or3c/t55 or3c/t80 or3t125 fclkc_del 10.34 11.01 7.88 8.11 8.60 9.15 10.07 6.41 6.58 6.95 7.34 7.96 5.40 5.58 5.94 6.33 6.94 ns ns ns ns ns
124 lucent technologies inc. data sheet june 1999 orca series 3c and 3t fpgas timing characteristics (continued) table 53 . general-pur p ose clock timin g characteristics ( internall y generated clock ) or3cxx commercial: v dd = 5.0 v 5%, 0 c < t a < 70 c; industrial: v dd = 5.0 v 10%, C40 c < t a < +85 c. or3txxx commercial: v dd = 3.0 v to 3.6 v, 0 c < t a < 70 c; industrial: v dd = 3.0 v to 3.6 v, C40 c < t a < +85 c. notes: this table represents the dela y for an internall y g enerated clock from the clock tree input in one of the four middle pics ( usin g psw routin g) on an y side of the device which is then distributed to the pfu/pio clock inputs. if the clock tree input used is located at an y other pic, see the results reported b y orca foundr y . this clock dela y is for a full y routed clock tree that uses the g eneral clock network. the dela y will be reduced if an y of the clock branches are not used. see pin-to-pin timin g in table 56 for clock dela y s of clocks input on g eneral i/o pins. device ( t j = 85 c, v dd = min ) symbol speed unit -4 -5 -6 -7 minmaxminmaxminmaxminmax or3t20 clk_del 4.22 3.46 2.84 ns or3t30 clk_del 4.29 3.48 2.87 ns or3c/t55 clk_del 5.34 4.41 3.53 2.93 ns or3c/t80 clk_del 5.49 4.52 3.57 2.98 ns or3t125 clk_del 4.80 3.71 3.13 ns
lucent technologies inc. 125 data sheet june 1999 orca series 3c and 3t fpgas timing characteristics (continued) table 54. or3cxx expressclk to output delay (pin-to-pin) or3cxx commercial: v dd = 5.0 v 5%, 0 c < t a < 70 c; industrial: v dd = 5.0 v 10%, C40 c < t a < +85 c; c l = 50 pf. or3txxx commercial: v dd = 3.0 v to 3.6 v, 0 c < t a < 70 c; industrial: v dd = 3.0 v to 3.6 v, C40 c < t a < +85 c;c l = 50 pf. notes: timin g is without the use of the pro g rammable clock mana g er ( pcm ) . this clock dela y is for a full y routed clock tree that uses the expressclk network. it includes both the input buffer dela y , the clock routin g to the pio clk input, the clock ? q of the ff, and the dela y throu g h the output buffer. the g iven timin g re q uires that the input clock pin be located at one of the six expressclk inputs of the device, and that a pio ff be used. 5-4846(f).a figure 76. expressclk to output delay description ( t j = 85 c, v dd = min ) device speed unit -4 -5 -6 -7 min max min max min max min max eclk middle input pin ? output pin ( fast ) or3t20 or3t30 or3c/t55 or3c/t80 or3t125 9.93 10.10 7.78 7.84 7.96 8.08 8.28 5.40 5.43 5.48 5.54 5.64 4.38 4.40 4.44 4.49 4.58 ns ns ns ns ns eclk middle input pin ? output pin ( slewlim ) or3t20 or3t30 or3c/t55 or3c/t80 or3t125 12.37 12.54 9.77 9.83 9.95 10.07 10.27 6.07 6.10 6.15 6.21 6.31 4.91 4.93 4.97 5.02 5.11 ns ns ns ns ns eclk middle input pin ? output pin ( sinklim ) or3t20 or3t30 or3c/t55 or3c/t80 or3t125 13.73 13.90 11.12 11.18 11.30 11.42 11.62 10.92 10.95 11.00 11.06 11.16 9.65 9.67 9.71 9.76 9.85 ns ns ns ns ns additional dela y if eclk corner pin used or3t20 or3t30 or3c/t55 or3c/t80 or3t125 1.97 1.97 1.91 1.91 1.91 1.91 1.90 1.80 1.90 2.09 2.28 2.57 1.58 1.67 1.84 2.02 2.29 ns ns ns ns ns output (50 pf load) q d eclk eclk pio ff clkcntrl
126 lucent technologies inc. data sheet june 1999 orca series 3c and 3t fpgas timing characteristics (continued) table 55 . or3cxx fast clock ( fclk ) to out p ut dela y ( pin-to-pin ) or3cxx commercial: v dd = 5.0 v 5%, 0 c < t a < 70 c; industrial: v dd = 5.0 v 10%, C40 c < t a < +85 c; c l = 50 pf. or3txxx commercial: v dd = 3.0 v to 3.6 v, 0 c < t a < 70 c; industrial: v dd = 3.0 v to 3.6 v, C40 c < t a < +85 c; c l = 50 pf. notes: timin g is without the use of the pro g rammable clock mana g er ( pcm ) . this clock dela y is for a full y routed clock tree that uses the primar y clock network. it includes both the input buffer dela y , the clock routin g to the pio clk input, the clock ? q of the ff, and the dela y throu g h the output buffer. the dela y will be reduced if an y of the clock branches are not used. the g iven timin g re q uires that the input clock pin be located at one of the six expressclk inputs of the device and that a pio ff be used. 5-4846(f).b figure 77. fast clock to output delay description ( t j = 85 c, v dd = min ) device speed unit -4 -5 -6 -7 minmaxminmaxminmaxminmax output not on same side of device as input clock (fast clock delays using expressclk inputs) eclk middle input pin ? output pin ( fast ) or3t20 or3t30 or3c/t55 or3c/t80 or3t125 14.68 15.30 11.13 11.35 11.81 12.33 13.20 7.94 8.01 8.18 8.36 8.68 6.40 6.48 6.66 6.85 7.19 ns ns ns ns ns eclk middle input pin ? output pin ( slewlim ) or3t20 or3t30 or3c/t55 or3c/t80 or3t125 17.11 17.74 13.12 13.33 13.80 14.32 15.19 8.61 8.68 8.85 9.04 9.35 6.93 7.01 7.19 7.38 7.72 ns ns ns ns ns eclk middle input pin ? output pin ( sinklim ) or3t20 or3t30 or3c/t55 or3c/t80 or3t125 18.47 19.10 14.47 14.68 15.15 15.67 16.54 13.46 13.53 13.70 13.88 14.20 11.67 11.75 11.93 12.12 12.46 ns ns ns ns ns additional dela y if eclk corner pin used or3t20 or3t30 or3c/t55 or3c/t80 or3t125 2.10 2.14 1.97 1.99 2.01 2.04 2.09 1.82 1.92 2.12 2.33 2.63 1.60 1.69 1.88 2.07 2.39 ns ns ns ns ns output (50 pf load) q d eclk fclk pio ff clkcntrl
lucent technologies inc. 127 data sheet june 1999 orca series 3c and 3t fpgas timing characteristics (continued) table 56 . or3cxx general s y stem clock ( sclk ) to out p ut dela y ( pin-to-pin ) or3cxx commercial: v dd = 5.0 v 5%, 0 c < t a < 70 c; industrial: v dd = 5.0 v 10%, C40 c < t a < +85 c; c l = 50 pf. or3txxx commercial: v dd = 3.0 v to 3.6 v, 0 c < t a < 70 c; industrial: v dd = 3.0 v to 3.6 v, C40 c < t a < +85 c; c l = 50 pf. note: this clock dela y is for a full y routed clock tree that uses the primar y clock network. it includes both the input buffer dela y , the clock routin g to the pio clk input, the clock ? q of the ff, and the dela y throu g h the output buffer. the dela y will be reduced if an y of the clock branches are not used. the g iven timin g re q uires that the input clock pin be located at one of the four center pics on an y side of the device and that a pio ff be used. for clock pins located at an y other pio, see the results reported b y orca foundr y . 5-4846(f) figure 78. system clock to output delay description ( t j = 85 c, v dd = min ) device speed unit -4 -5 -6 -7 min max min max min max min max output on same side of device as input clock (system clock delays using general user i/o inputs) clock input pin ( mid-pic ) ? output pin ( fast ) or3t20 or3t30 or3c/t55 or3c/t80 or3t125 14.91 15.71 11.35 11.63 12.17 12.80 13.69 7.74 7.93 8.28 8.66 9.24 6.10 6.27 6.59 6.95 7.49 ns ns ns ns ns clock input pin ( mid-pic ) ? output pin ( slewlim ) or3t20 or3t30 or3c/t55 or3c/t80 or3t125 17.34 18.14 13.34 13.62 14.16 14.79 15.68 8.42 8.60 8.95 9.34 9.91 6.63 6.80 7.12 7.48 8.02 ns ns ns ns ns clock input pin ( mid-pic ) ? output pin ( sinklim ) or3t20 or3t30 or3c/t55 or3c/t80 or3t125 18.70 19.51 14.69 14.97 15.51 16.14 17.03 13.26 13.45 13.80 14.18 14.76 11.37 11.54 11.86 12.22 12.76 ns ns ns ns ns additional dela y if non-mid-pic used as clock pin or3t20 or3t30 or3c/t55 or3c/t80 or3t125 0.41 0.63 0.16 0.20 0.36 0.55 1.11 0.18 0.21 0.37 0.57 1.05 0.17 0.20 0.35 0.55 1.02 ns ns ns ns ns output not on same side of device as input clock (system clock delays using general user i/o inputs) additional dela y if output not on same side as input clock pin or3t20 or3t30 or3c/t55 or3c/t80 or3t125 0.41 0.63 0.16 0.20 0.36 0.55 1.11 0.18 0.21 0.37 0.57 1.05 0.17 0.20 0.35 0.55 1.02 ns ns ns ns ns output ( 50 pf load ) q d sclk pio ff
128 lucent technologies inc. data sheet june 1999 orca series 3c and 3t fpgas timing characteristics (continued) table 57 . or3c/txxx in p ut to ex p ressclk ( eclk ) fast-ca p ture setu p /hold time ( pin-to-pin ) or3cxx commercial: v dd = 5.0 v 5%, 0 c < t a < 70 c; industrial: v dd = 5.0 v 10%, C40 c < t a < +85 c. or3txxx commercial: v dd = 3.0 v to 3.6 v, 0 c < t a < 70 c; industrial: v dd = 3.0 v to 3.6 v, C40 c < t a < +85 c. note: the pin-to-pin timin g parameters in this table should be used instead of results reported b y orca foundr y . the eclk dela y s are to all of the pios on one side of the device for middle pin input, or two sides of the device for corner pin input. the d ela y includes both the input buffer dela y and the clock routin g to the pio clock input. description ( t j = 85 c, v dd = min ) device speed unit -4 -5 -6 -7 min max min max min max min max input to eclk setup time ( middle eclk pin ) or3t20 or3t30 or3c/t55 or3c/t80 or3t125 1.36 1.25 1.34 1.30 1.22 1.14 1.03 0.88 0.86 0.83 0.80 0.76 0.83 0.82 0.80 0.77 0.74 ns ns ns ns ns input to eclk setup time ( middle eclk pin, dela y ed data input ) or3t20 or3t30 or3c/t55 or3c/t80 or3t125 6.91 6.79 6.30 6.27 6.19 6.11 6.00 5.32 5.30 5.27 5.24 5.20 5.98 5.97 5.95 5.93 5.90 ns ns ns ns ns input to eclk setup time ( corner eclk pin ) or3t20 or3t30 or3c/t55 or3c/t80 or3t125 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 ns ns ns ns ns input to eclk setup time ( corner eclk pin, dela y ed data input ) or3t20 or3t30 or3c/t55 or3c/t80 or3t125 4.94 4.82 4.39 4.35 4.28 4.21 4.10 3.51 3.40 3.18 2.98 2.63 4.41 4.31 4.11 3.91 3.61 ns ns ns ns ns input to eclk hold time ( middle eclk pin ) or3t20 or3t30 or3c/t55 or3c/t80 or3t125 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 ns ns ns ns ns input to eclk hold time ( middle eclk pin, dela y ed data input ) or3t20 or3t30 or3c/t55 or3c/t80 or3t125 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 ns ns ns ns ns
lucent technologies inc. 129 data sheet june 1999 orca series 3c and 3t fpgas timing characteristics (continued) table 57 . or3c/txxx in p ut to ex p ressclk ( eclk ) fast-ca p ture setu p /hold time ( pin-to-pin ) (continued) or3cxx commercial: v dd = 5.0 v 5%, 0 c < t a < 70 c; industrial: v dd = 5.0 v 10%, C40 c < t a < +85 c. or3txxx commercial: v dd = 3.0 v to 3.6 v, 0 c < t a < 70 c; industrial: v dd = 3.0 v to 3.6 v, C40 c < t a < +85 c. notes: the pin-to-pin timin g parameters in this table should be used instead of results reported b y orca foundr y . the eclk dela y s are to all of the pios on one side of the device for middle pin input, or two sides of the device for corner pin input. the d ela y includes both the input buffer dela y and the clock routin g to the pio clock input. 5-4847(f).b fi g ure 79. in p ut to ex p ressclk setu p /hold time description ( t j = 85 c, v dd = min ) device speed unit -4 -5 -6 -7 minmaxminmaxminmaxminmax input to eclk hold time ( corner eclk pin ) or3t20 or3t30 or3c/t55 or3c/t80 or3t125 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.80 0.00 0.00 0.00 0.00 1.10 0.00 0.00 ns ns ns ns ns input to eclk hold time ( corner eclk pin, dela y ed data input ) or3t20 or3t30 or3c/t55 or3c/t80 or3t125 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 ns ns ns ns ns q d clk input pio eclk latch clkcntrl eclk
130 lucent technologies inc. data sheet june 1999 orca series 3c and 3t fpgas timing characteristics (continued) table 58. or3c/txxx input to fast clock setup/hold time (pin-to-pin) or3cxx commercial: v dd = 5 .0 v 5%, 0 c < t a < 70 c; industrial: v dd = 5.0 v 10%, C40 c < t a < +85 c. or3txxx commercial: v dd = 3.0 v to 3.6 v, 0 c < t a < 70 c; industrial: v dd = 3.0 v to 3.6 v, C40 c < t a < +85 c. notes: the pin-to-pin timin g parameters in this table should be used instead of results reported b y orca foundr y . the fclk dela y s are for a full y routed clock tree that uses the expressclk input into the fast clock network. it includes both the input buffer dela y and the clock routin g to the pfu clk input. the dela y will be reduced if an y of the clock branches are not used. description ( t j = 85 c, v dd = min ) device speed unit -4 -5 -6 -7 minmaxminmaxminmaxminmax output not on same side of device as input clock (fast clock delays using expressclk inputs) input to fclk setup time ( middle eclk pin ) or3t20 or3t30 or3c/t55 or3c/t80 or3t125 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 ns ns ns ns ns input to fclk setup time ( middle eclk pin, dela y ed data input ) or3t20 or3t30 or3c/t55 or3c/t80 or3t125 0.29 0.14 0.80 0.74 0.62 0.50 0.22 0.58 0.55 0.51 0.46 0.33 2.20 2.17 2.11 2.06 1.90 ns ns ns ns ns input to fclk setup time ( corner eclk pin ) or3t20 or3t30 or3c/t55 or3c/t80 or3t125 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 ns ns ns ns ns input to fclk setup time ( corner eclk pin, dela y ed data input ) or3t20 or3t30 or3c/t55 or3c/t80 or3t125 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 ns ns ns ns ns input to fclk hold time ( middle eclk pin ) or3t20 or3t30 or3c/t55 or3c/t80 or3t125 6.33 6.95 4.29 4.50 4.97 5.49 6.36 3.72 3.80 3.96 4.15 4.47 3.27 3.35 3.52 3.72 4.05 ns ns ns ns ns
lucent technologies inc. 131 data sheet june 1999 orca series 3c and 3t fpgas timing characteristics (continued) table 58. or3c/txxx input to fast clock setup/hold time (pin-to-pin) (continued) or3cxx commercial: v dd = 5 .0 v 5%, 0 c < t a < 70 c; industrial: v dd = 5.0 v 10%, C40 c < t a < +85 c. or3txxx commercial: v dd = 3.0 v to 3.6 v, 0 c < t a < 70 c; industrial: v dd = 3.0 v to 3.6 v, C40 c < t a < +85 c. notes: the pin-to-pin timin g parameters in this table should be used instead of results reported b y orca foundr y . the fclk dela y s are for a full y routed clock tree that uses the expressclk input into the fast clock network. it includes both the input buffer dela y and the clock routin g to the pfu clk input. the dela y will be reduced if an y of the clock branches are not used. 5-4847(f).a figure 80. input to fast clock setup/hold time description ( t j = 85 c, v dd = min ) device speed unit -4 -5 -6 -7 minmaxminmaxminmaxminmax input to fclk hold time ( middle eclk pin, dela y ed data input ) or3t20 or3t30 or3c/t55 or3c/t80 or3t125 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 ns ns ns ns ns input to fclk hold time ( corner eclk pin ) or3t20 or3t30 or3c/t55 or3c/t80 or3t125 8.43 9.09 6.26 6.49 6.98 7.53 8.45 5.54 5.72 6.09 6.47 7.10 4.88 5.04 5.40 5.79 6.40 ns ns ns ns ns input to fclk hold time ( corner eclk pin, dela y ed data input ) or3t20 or3t30 or3c/t55 or3c/t80 or3t125 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 ns ns ns ns ns q d eclk input pio ff clkcntrl fclk
132 lucent technologies inc. data sheet june 1999 orca series 3c and 3t fpgas timing characteristics (continued) table 59. or3c/txxx input to general system clock (sclk) setup/hold time (pin-to-pin) or3cxx commercial: v dd = 5.0 v 5%, 0 c < t a < 70 c; industrial: v dd = 5.0 v 10%, C40 c < t a < +85 c. or3txxx commercial: v dd = 3.0 v to 3.6 v, 0 c < t a < 70 c; industrial: v dd = 3.0 v to 3.6 v, C40 c < t a < +85 c. notes: the pin-to-pin timin g parameters in this table should be used instead of results reported b y orca foundr y . this clock dela y is for a full y routed clock tree that uses the clock network. it includes both the input buffer dela y and the clock routin g to the pio ff clk input. the dela y will be reduced if an y of the clock branches are not used. the g iven setup ( dela y ed and no dela y) and hold ( dela y ed ) timin g allows the input clock pin to be located in an y pio on an y side of the device, but a pio ff must be used. the hold ( no dela y) timin g assumes the clock pin is located at one of the four middle pics on an y side of the device and that a pio ff is used. if the clock pin is located elsewhere, then the last parameter in the table must be added to the hold ( no dela y) timin g . 5-4847(f) figure 81. input to system clock setup/hold time description ( t j = 85 c, v dd = min ) device speed unit -4 -5 -6 -7 min max min max min max min max input to sclk setup time or3t20 or3t30 or3c/t55 or3c/t80 or3t125 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 ns ns ns ns ns input to sclk setup time ( dela y ed data input ) or3t20 or3t30 or3c/t55 or3c/t80 or3t125 0.99 0.79 1.33 1.22 1.09 0.93 0.78 1.47 1.40 1.33 1.26 1.19 3.09 3.03 2.97 2.91 2.86 ns ns ns ns ns input to sclk hold time or3t20 or3t30 or3c/t55 or3c/t80 or3t125 6.82 7.62 4.74 5.01 5.56 6.19 7.07 3.64 3.83 4.18 4.56 5.14 3.04 3.22 3.54 3.89 4.44 ns ns ns ns ns input to sclk hold time ( dela y ed data input ) or3t20 or3t30 or3c/t55 or3c/t80 or3t125 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 ns ns ns ns ns additional hold time if non- mid-pic used as sclk pin ( no dela y on data input ) or3t20 or3t30 or3c/t55 or3c/t80 or3t125 0.41 0.63 0.16 0.20 0.36 0.55 1.11 0.18 0.21 0.37 0.57 1.05 0.17 0.20 0.35 0.55 1.02 ns ns ns ns ns q d sclk input pio ff
lucent technologies inc. 133 data sheet june 1999 orca series 3c and 3t fpgas timing characteristics (continued) configuration timing table 60. general configuration mode timing characteristics or3cxx commercial: v dd = 5.0 v 5%, 0 c < t a < 70 c; industrial: v dd = 5.0 v 10%, C40 c < t a < +85 c. or3txxx commercial: v dd = 3.0 v to 3.6 v, 0 c < t a < 70 c; industrial: v dd = 3.0 v to 3.6 v, C40 c < t a < +85 c. * not applicable to as y nchronous peripheral mode. parameter symbol min max unit all configuration modes m [ 3:0 ] setup time to init hi g htsmode0.00ns m [ 3:0 ] hold time from init hi g h thmode 600.00 ns reset pulse width low to start reconfi g uration trw 50.00 ns prgm pulse width low to start reconfi g uration tpgw 50.00 ns master and as y nchronous peripheral modes power-on reset dela y cclk period ( m3 = 0 ) ( m3 = 1 ) confi g uration latenc y ( autoincrement mode ) : or3t20 ( m3 = 0 ) ( m3 = 1 ) or3t30 ( m3 = 0 ) ( m3 = 1 ) or3c/t55 ( m3 = 0 ) ( m3 = 1 ) or3c/t80 ( m3 = 0 ) ( m3 = 1 ) or3t125 ( m3 = 0 ) ( m3 = 1 ) tpo tcclk tcl 15.70 60.00 480.00 11.50 92.10 15.10 121.00 23.20 185.00 33.70 270.00 52.30 418.00 52.40 200.00 1600.00 38.40* 307.00* 50.40* 403.30* 77.40* 619.00* 113.00* 900.00* 175.00* 1395.00* ms ns ns ms ms ms ms ms ms ms ms ms ms microprocessor (mpi) mode power-on reset dela y confi g uration latenc y ( autoincrement mode ) : or3t20 or3t30 or3c/t55 or3c/t80 or3t125 tpo tcl 15.70 27413 35445 53341 76317 116581 52.40 ms write c y cles write c y cles write c y cles write c y cles write c y cles partial reconfi g uration ( explicit mode ) : or3t20 or3t30 or3c/t55 or3c/t80 or3t125 tpr 32 36 43 51 62 write c y cles write c y cles write c y cles write c y cles write c y cles slave serial mode power-on reset dela y cclk period or3cxx or3txxx confi g uration latenc y ( autoincrement mode ) : or3t20 or3t30 or3c55 OR3T55 or3c80 or3t80 or3t125 tpo tcclk tcl 3.90 40 15 2.80 3.80 15.50 5.80 22.50 8.40 13.09 13.10 ms ns ns ms ms ms ms ms ms ms
134 lucent technologies inc. data sheet june 1999 orca series 3c and 3t fpgas timing characteristics (continued) table 60. general confi g uration mode timin g characteristics (continued) or3cxx commercial: v dd = 5.0 v 5%, 0 c < t a < 70 c; industrial: v dd = 5.0 v 10%, C40 c < t a < +85 c. or3txxx commercial: v dd = 3.0 v to 3.6 v, 0 c < t a < 70 c; industrial: v dd = 3.0 v to 3.6 v, C40 c < t a < +85 c. note: t po is tri gg ered when v dd reaches between 3.0 v to 4.0 v for the or3cxx and between 2.7 v and 3.0 v for the or3txxx. parameter symbol min max unit slave parallel mode power-on reset dela y cclk period: or3cxx or3txxx confi g uration latenc y ( normal mode ) : or3t20 or3t30 or3c55 OR3T55 or3c80 or3t80 or3t125 t po t cclk t cl 3.90 40.00 15.00 0.36 0.47 1.94 0.72 2.81 1.05 1.64 13.10 ms ns ns ms ms ms ms ms ms ms partial reconfi g uration ( explicit mode ) : or3t20 or3t30 or3c55 OR3T55 or3c80 or3t80 or3t125 t pr 0.48 0.54 1.72 0.65 2.04 0.77 0.93 s/frame s/frame s/frame s/frame s/frame s/frame s/frame init timin g init hi g h to cclk dela y : slave parallel slave serial master serial: ( m3 = 1 ) ( m3 = 0 ) master parallel: ( m3 = 1 ) ( m3 = 0 ) t init_cclk 1.00 1.00 1.00 0.50 4.80 1.00 3.40 2.00 16.20 3.60 s s s s s s initialization latenc y ( prgm hi g h to init hi g h ) : or3t20 or3t30 or3c/t55 or3c/t80 or3t125 t il 0.21 0.24 0.30 0.36 0.45 0.68 0.79 1.00 1.20 1.50 ms ms ms ms ms init hi g h to wr , as y nchronous peripheral t init_wr 2.00 s
lucent technologies inc. 135 data sheet june 1999 orca series 3c and 3t fpgas timing characteristics (continued) 5-4531(f) figure 82. general configuration mode timing diagram v dd cclk m[3:0] prgm init t po + t il t il t cclk t smode t hmode t init_clk done t cl t pgw
136 lucent technologies inc. data sheet june 1999 orca series 3c and 3t fpgas timing characteristics (continued) table 61 . master serial confi g uration mode timin g characteristics or3cxx commercial: v dd = 5.0 v 5%, 0 c < t a < 70 c; industrial: v dd = 5.0 v 10%, C40 c < t a < +85 c. or3txxx commercial: v dd = 3.0 v to 3.6 v, 0 c < t a < 70 c; industrial: v dd = 3.0 v to 3.6 v, C40 c < t a < +85 c. * data g ets clocked out from an external serial rom. the clock to data dela y of the serial rom must be less than the cclk fre q uenc y since the data available out of the serial rom must be setup and waitin g to be clocked into the fpga before the next cclk risin g ed g e. note: serial confi g uration data is transmitted out on dout on the fallin g ed g e of cclk after it is input on din. 5-4532(f) figure 83. master serial configuration mode timing diagram parameter s y mbol min max unit din setup time* t s 60.00 ns din hold time t h 0.00 ns cclk fre q uenc y ( m3 = 0 ) f c 5.00 16.67 mhz cclk fre q uenc y ( m3 = 1 ) f c 0.63 2.08 mhz cclk to dout dela y t d 5.00ns din cclk dout t s t h bit n t d bit n
lucent technologies inc. 137 data sheet june 1999 orca series 3c and 3t fpgas timing characteristics (continued) table 62 . master parallel confi g uration mode timin g characteristics or3cxx commercial: v dd = 5.0 v 5%, 0 c < t a < 70 c; industrial: v dd = 5.0 v 10%, C40 c < t a < +85 c. or3txxx commercial: v dd = 3.0 v to 3.6 v, 0 c < t a < 70 c; industrial: v dd = 3.0 v to 3.6 v, C40 c < t a < +85 c. notes: the rclk period consists of seven cclks for rclk low and one cclk for rclk hi g h. serial data is transmitted out on dout 1.5 cclk c y cles after the b y te is input on d[7:0]. 5-6764(f) figure 84. master parallel configuration mode timing diagram parameter s y mbol min max unit rclk to address valid t av 60.00 ns d [ 7:0 ] setup time to rclk hi g ht s 60.00 ns d [ 7:0 ] hold time to rclk hi g ht h 0.00 ns rclk low time ( m3 = 0 ) t cl 7.00 7.00 cclk c y cles rclk hi g h time ( m3 = 0 ) t ch 1.00 1.00 cclk c y cles rclk low time ( m3 = 1 ) t cl 7.00 7.00 cclk c y cles rclk hi g h time ( m3 = 1 ) t ch 1.00 1.00 cclk c y cles cclk to dout t d 5.00ns a[17:0] rclk d[7:0] t cl t ch t av cclk dout t h t s byte n byte n + 1 d0 d1 d2 d3 d4 d5 d6 d7 t d
138 lucent technologies inc. data sheet june 1999 orca series 3c and 3t fpgas timing characteristics (continued) table 63 . as y nchronous peri p heral confi g uration mode timin g characteristics or3cxx commercial: v dd = 5.0 v 5%, 0 c < t a < 70 c; industrial: v dd = 5.0 v 10%, C40 c < t a < +85 c. or3txxx commercial: v dd = 3.0 v to 3.6 v, 0 c < t a < 70 c; industrial: v dd = 3.0 v to 3.6 v, C40 c < t a < +85 c. * this parameter is valid whether the end of not rdy is determined from the rdy pin or from the d7 pin. notes: serial data is transmitted out on dout on the fallin g ed g e of cclk after the b y te is input on d[7:0]. d[6:0] timin g is the same as the write data portion of the d7 waveform because d[6:0] are not enabled b y rd . 5-4533(f) figure 85. asynchronous peripheral configuration mode timing diagram parameter symbol min max unit wr , cs0 , and cs1 pulse width t wr 50.00 ns d [ 7:0 ] setup time: 3cxx 3txxx t s 20.00 10.50 ns ns d [ 7:0 ] hold time t h 0.00 ns rdy dela y t rdy 40.00 ns rdy low t b 1.00 8.00 cclk periods earliest wr after rdy goes hi g h* t wr2 0.00 ns rd to d7 enable/disable t den 40.00 ns cclk to dout t d 5.00ns cs1 d7 cclk dout cs0 rdy d0 d1 d2 t b t wr t s t h t rdy wr d7 t d previous byte t wr2 write data d3 t den t den rd
lucent technologies inc. 139 data sheet june 1999 orca series 3c and 3t fpgas timing characteristics (continued) table 64. slave serial configuration mode timing characteristics or3cxx commercial: v dd = 5.0 v 5%, 0 c < t a < 70 c; industrial: v dd = 5.0 v 10%, C40 c < t a < +85 c. or3txxx commercial: v dd = 3.0 v to 3.6 v, 0 c < t a < 70 c; industrial: v dd = 3.0 v to 3.6 v, C40 c < t a < +85 c. note: serial confi g uration data is transmitted out on dout on the fallin g ed g e of cclk after it is input on din. 5-4535(f) . figure 86. slave serial configuration mode timing diagram parameter s y mbol min max unit din setup time: 3cxx 3txxx t s 20.00 10.50 ns ns din hold time t h 0.00 ns cclk hi g h time: 3cxx 3txxx t ch 20.00 7.00 ns ns cclk low time: 3cxx 3txxx t cl 20.00 7.00 ns ns cclk fre q uenc y : 3cxx 3txxx f c 25.00 66.00 mhz mhz cclk to dout t d 20.00 ns din cclk dout t d t s t h t cl t ch bit n bit n
140 lucent technologies inc. data sheet june 1999 orca series 3c and 3t fpgas timing characteristics (continued) table 65. slave parallel configuration mode timing characteristics or3cxx commercial: v dd = 5.0 v 5%, 0 c < t a < 70 c; industrial: v dd = 5.0 v 10%, C40 c < t a < +85 c. or3txxx commercial: v dd = 3.0 v to 3.6 v, 0 c < t a < 70 c; industrial: v dd = 3.0 v to 3.6 v, C40 c < t a < +85 c. note: dais y -chainin g of fpgas is not supported in this mode. 5-2848(f) figure 87. slave parallel configuration mode timing diagram parameter s y mbol min max unit cs0 , cs1, wr setup time t s1 40.00 ns cs0 , cs1, wr hold time t h1 20.00 ns d [ 7:0 ] setup time: 3cxx 3txxx t s2 20.00 7.00 ns ns d [ 7:0 ] hold time t h2 0.00 ns cclk hi g h time: 3cxx 3txxx t ch 20.00 7.00 ns ns cclk low time: 3cxx 3txxx t cl 20.00 7.00 ns ns cclk fre q uenc y : 3cxx 3txxx f c 25.00 66.00 mhz mhz t s1 t s2 t h2 cs1 cclk d[7:0] cs0 wr t cl t ch t h1
lucent technologies inc. 141 data sheet june 1999 orca series 3c and 3t fpgas timing characteristics (continued) microprocessor interface (mpi) configuration timing characteristics for configuration timing using the mpi, consult table 49. see figures 67 through 74 for mpi timing diagrams.
142 lucent technologies inc. data sheet june 1999 orca series 3c and 3t fpgas timing characteristics (continued) readback timing table 66 . readback timin g characteristics or3cxx commercial: v dd = 5.0 v 5%, 0 c < t a < 70 c; industrial: v dd = 5.0 v 10%, C40 c < t a < +85 c. or3txxx commercial: v dd = 3.0 v to 3.6 v, 0 c < t a < 70 c; industrial: v dd = 3.0 v to 3.6 v, C40 c < t a < +85 c. 5-4536(f) figure 88. readback timing diagram parameter s y mbol min max unit rd_cfg to cclk setup time t s 50.00 ns rd_cfg hi g h width to abort readback t rba 2 cclk c y cles cclk low time t cl 40.00 ns cclk hi g h time t ch 40.00 ns cclk fre q uenc y f c 12.50 mhz cclk to rd_data dela y t d 40.00 ns t d t ch cclk rd_data t s t cl rd_cfg bit 0 bit 1 bit 0 t rba
lucent technologies inc. 143 data sheet june 1999 orca series 3c and 3t fpgas input/output buffer measurement conditions note: switch to v dd for t plz /t pzl ; switch to gnd for t phz /t pzh . 5-3234(f) figure 89. ac test loads 5-3233.a(f) fi g ure 90. out p ut buffer dela y s 5-3235(f) fi g ure 91. in p ut buffer dela y s 50 pf a. load used to measure propagation delay to the output under test to the output under test 50 pf v cc gnd 1 k w b. load used to measure rising/falling edges v dd t phh v dd /2 v ss out[i] pa d out 1.5 v 0.0 v t pll pad out[i] ac test loads (shown above) ts[i] out 0.0 v 1.5 v t phh t pll pa d in[i] in 3.0 v v ss v dd /2 v dd pa d i n in[i]
144 144 lucent technologies inc. data sheet june 1999 orca series 3c and 3t fpgas output buffer characteristics or3cxx 5-4634(f) fi g ure 92. sinklim ( t j = 25 c, v dd = 5.0 v ) 5-4636(f) fi g ure 93. slewlim ( t j = 25 c, v dd = 5.0 v ) 5-4638(f) fi g ure 94. fast ( t j = 25 c, v dd = 5.0 v ) 5-4635(c) fi g ure 95. sinklim ( t j = 125 c, v dd = 4.5 v ) 5-4637(f) fi g ure 96. slewlim ( t j = 125 c, v dd = 4.5 v ) 5-4639(f) fi g ure 97. fast ( t j = 125 c, v dd = 4.5 v ) 70 60 50 40 30 20 10 0 output current, i o (ma) 012345 output voltage, v o (v) i ol i oh 250 225 150 100 50 0 output current, i o (ma) 0123 4 output voltage, v o (v) i ol i oh 5 200 175 125 75 25 250 225 150 100 50 0 output current, i o (ma) 0123 4 output voltage, v o (v) i ol i oh 5 200 175 125 75 25 50 40 30 20 10 0 output current, i o (ma) 01 2 3 4 output voltage, v o (v) i ol i oh 5 150 125 100 75 50 0 output current, i o (ma) 01 2 3 4 output voltage, v o (v) i ol i oh 25 175 125 100 75 50 0 output current, i o (ma) 01 2 3 4 output voltage, v o (v) i ol i oh 25 150
lucent technologies inc. 145 data sheet june 1999 orca series 3c and 3t fpgas output buffer characteristics (continued) or3txxx 5-6865(f) fi g ure 98. sinklim ( t j = 25 c, v dd = 3.3 v ) 5-6967(f) fi g ure 99. slewlim ( t j = 25 c, v dd = 3.3 v ) 5-6867(f) fi g ure 100. fast ( t j = 25 c, v dd = 3.3 v ) 5-6866(f) fi g ure 101. sinklim ( t j = 125 c, v dd = 3.0 v ) 5-6868(f) fi g ure 102. slewlim ( t j = 125 c, v dd = 3.0 v ) 5-6868(f) fi g ure 103. fast ( t j = 125 c, v dd = 3.0 v ) 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 0 20 40 60 110 output voltage, v o (v) i ol 70 50 30 10 i oh output current, i o (ma) 80 90 100 0.0 0.5 1.0 1.5 2.0 2.5 3.0 0 40 80 output voltage, v o (v) i ol 100 60 20 i oh output current, i o (ma) 120 140 3.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 0 40 80 output voltage, v o (v) i ol 100 60 20 i oh output current, i o (ma) 120 140 3.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 0 20 40 60 output voltage, v o (v) i ol 70 50 30 10 i oh output current, i o (ma) 80 90 0.0 0.5 1.0 1.5 2.0 2.5 3.0 0 40 80 output voltage, v o (v) i ol 100 60 20 i oh output current, i o (ma) 120 0.0 0.5 1.0 1.5 2.0 2.5 3.0 0 40 80 output voltage, v o (v) i ol 100 60 20 i oh output current, i o (ma) 120
146 146 lucent technologies inc. data sheet june 1999 orca series 3c and 3t fpgas estimating power dissipation or3cxx the total operating power dissipated is estimated by summing the standby (i ddsb ), internal, and external power dissipated. the internal and external power is the power consumed in the plcs and pics, respec- tively. in general, the standby power is small and may be neglected. the total operating power is as follows: p t = s p plc + s p pic the internal operating power is made up of two parts: clock generation and pfu output power. the pfu out- put power can be estimated based upon the number of pfu outputs switching when driving an average fan-out of two: p pfu = 0.136 mw/mhz for each pfu output that switches, 0.136 mw/mhz needs to be multiplied times the frequency (in mhz) that the output switches. generally, this can be esti- mated by using one-half the clock rate, multiplied by some activity factor; for example, 20%. the power dissipated by the clock generation circuitry is based upon four parts: the fixed clock power, the power/clock branch row or column, the clock power dis- sipated in each pfu that uses this particular clock, and the power from the subset of those pfus that are con- figured as synchronous memory. therefore, the clock power can be calculated for the four parts using the fol- lowing equations: or3c55 clock power p= [ 0.183 mw/mhz + ( 0.235 mw/mhz/branch ) ( # branches ) + ( 0.033 mw/mhz/pfu ) ( # pfus ) + ( 0.008 mw/mhz/pio ( # pios )] for a quick estimate, the worst-case (typical circuit) or3c55 clock power ? 14.64 mw/mhz. or3c80 clock power p= [ 0.224 mw/mhz + ( 0.288 mw/mhz/branch ) ( # branches ) + ( 0.033 mw/mhz/pfu ) ( # pfus ) + ( 0.008 mw/mhz/pio ( # pios )] for a quick estimate, the worst-case (typical circuit) or3c80 clock power ? 21.06 mw/mhz. the power dissipated in a pic is the sum of the power dissipated in the four pios in the pic. this consists of power dissipated by inputs and ac power dissipated by outputs. the power dissipated in each pio depends on whether it is configured as an input, output, or input/ output. if a pio is operating as an output, then there is a power dissipation component for p in , as well as p out . this is because the output feeds back to the input. the power dissipated by a ttl input buffer is estimated as: p ttl = 2.2 mw + 0.17 mw/mhz the power dissipated by an input buffer is estimated as: p cmos = 0.17 mw/mhz the ac power dissipation from an output or bidirec- tional is estimated by the following: p out = ( c l + 8.8 pf ) x v dd 2 x f watts where the unit for c l is farads, and the unit for f is hz. as an example of estimating power dissipation, sup- pose that a fully utilized or3c55 has an average of six outputs for each of the 324 pfus, that 10 clock branches are used so that the clock is driven to the entire plc array, that 150 of the 324 pfus have ffs clocked at 40 mhz, and that the pfu outputs have an average activity factor of 20%. twenty ttl-configured inputs, 20 cmos-configured inputs, 32 outputs driving 30 pf loads, and 16 bidirec- tional i/os driving 50 pf loads are also generated from the 40 mhz clock with an average activity factor of 20%. all of the output pios are registered, and 30 of the input pios are registered. the worst-case (v dd = 5.25 v) power dissipation is estimated as follows: p pfu = 324 x 6 ( 0.136 mw/mhz x 20 mhz x 20% ) = 1057.54 mw p clk = [ 0.183 mw/mhz + ( 0.235 mw/mhz C branch ) ( 10 branches ) + ( 0.033 mw/mhz C pfu ) ( 150 pfus ) + ( 0.008 mw/mhz/pio ( 58 pios )] = 317.88 mw p ttl = 20 x [ 2.2 mw + ( 0.17 mw/mhz x 20 mhz x 20% )] = 57.6 mw p cmos = 20 x [ 0.17 mw x 20 mhz x 20% ] = 13.6 mw p out = 32 x [( 30 pf + 8.8 pf ) x ( 5.25 ) 2 x 20 mhz x 20% ] =136.89 mw p bid = 16 x [( 50 pf + 8.8 pf ) x ( 5.25 ) 2 x 20 mhz x 20% ] = 103.72 mw to t a l = 1.69 w
lucent technologies inc. 147 data sheet june 1999 orca series 3c and 3t fpgas estimating power dissipation (continued) or3txxx (preliminary information) the total operating power dissipated is estimated by summing the standby (i ddsb ), internal, and external power dissipated. the internal and external power is the power consumed in the plcs and pics, respec- tively. in general, the standby power is small and may be neglected. the total operating power is as follows: p t = s p plc + s p pic the internal operating power is made up of two parts: clock generation and pfu output power. the pfu out- put power can be estimated based upon the number of pfu outputs switching when driving an average fan-out of two: p pfu = 0.068 mw/mhz for each pfu output that switches, 0.068 mw/mhz needs to be multiplied times the frequency (in mhz) that the output switches. generally, this can be esti- mated by using one-half the clock rate, multiplied by some activity factor; for example, 20%. the power dissipated by the clock generation circuitry is based upon four parts: the fixed clock power, the power/clock branch row or column, the clock power dis- sipated in each pfu that uses this particular clock, and the power from the subset of those pfus configured as synchronous memory. therefore, the clock power can be calculated for the four parts using the following equations. or3t20 clock power p= [ 0.38 mw/mhz + ( 0.045 mw/mhz/branch ) ( # branches ) + ( 0.015 mw/mhz/pfu ) ( # pfus ) + ( 0.004 mw/mhz/pio ( # pios )] for a quick estimate, the worst-case (typical circuit) or3t20 clock power ? 2.92 mw/mhz. or3t30 clock power p= [ 0.53 mw/mhz + ( 0.061 mw/mhz/branch ) ( # branches ) + ( 0.015 mw/mhz/pfu ) ( # pfus ) + ( 0.004 mw/mhz/pio ( # pios )] for a quick estimate, the worst-case (typical circuit) or3t30 clock power ? 3.98 mw/mhz. OR3T55 clock power p= [ 0.88 mw/mhz + ( 0.102 mw/mhz/branch ) ( # branches ) + ( 0.015 mw/mhz/pfu ) ( # pfus ) + ( 0.004 mw/mhz/pio ( # pios )] for a quick estimate, the worst-case (typical circuit) OR3T55 clock power ? 6.58 mw/mhz. or3t80 clock power p= [ 0.107 mw/mhz + ( 0.124 mw/mhz/branch ) ( # branches ) + ( 0.015 mw/mhz/pfu ) ( # pfus ) + ( 0.004 mw/mhz/pio ( # pios )] for a quick estimate, the worst-case (typical circuit) or3t80 clock power ? 9.47 mw/mhz. or3t125 clock power p= [ 0.167 mw/mhz + ( 0.193 mw/mhz/branch ) ( # branches ) + ( 0.015 mw/mhz/pfu ) ( # pfus ) + ( 0.004 mw/mhz/pio ( # pios )] for a q uick estimate, the worst-case ( t y pical circuit ) or3t125 clock power ? 15.44 mw/mhz. the power dissipated in a pic is the sum of the power dissipated in the four pios in the pic. this consists of power dissipated by inputs and ac power dissipated by outputs. the power dissipated in each pio depends on whether it is configured as an input, output, or input/ output. if a pio is operating as an output, then there is a power dissipation component for p in , as well as p out . this is because the output feeds back to the input. the power dissipated by an input buffer (v ih = v dd C 0.3 v or higher) is estimated as: p in = 0.09 mw/mhz the ac power dissipation from an output or bidirec- tional is estimated by the following: p out = ( c l + 8.8 pf ) x v dd 2 x f watts where the unit for c l is farads, and the unit for f is hz.
148 lucent technologies inc. data sheet june 1999 orca series 3c and 3t fpgas estimating power dissipation (continued) as an example of estimating power dissipation, suppose that a fully utilized or3t80 has an average of six outputs for each of the 484 pfus, that 12 clock branches are used so that the clock is driven to the entire plc array, that 250 of the 484 pfus have ffs clocked at 40 mhz, and that the pfu outputs have an average activity factor of 20%. eighty inputs, 40 of them used as 5 v tolerant inputs, 50 outputs driving 30 pf loads, and 30 bidirectional i/os driving 50 pf loads are also generated from the 40 mhz clock with an average activity factor of 20%. all of the output pios are registered, and 30 of the input pios are registered. the worst-case (v dd = 3.6 v) power dissipation is estimated as follows: p pfu = 484 x 6 ( 0.068 mw/mhz x 20 mhz x 20% ) = 789.9 mw p clk = [ 0.107 mw/mhz + ( 0.09 mw/mhz C branch ) ( 12 branches ) + ( 0.015 mw/mhz C pfu ) ( 250 pfus ) + ( 0.004 mw/mhz/pio ) ( 110 pios )] = 230.43 mw p in = 80 x [ 0.09 mw/mhz x 20 mhz x 20% ] = 28.8 mw p out = 50 x [( 30 pf + 8.8 pf ) x ( 3.6 ) 2 x 20 mhz x 20% ] = 100.57 mw p bid = 30 x [( 50 pf + 8.8 pf ) x ( 3.6 ) 2 x 20 mhz x 20% ] = 91.45 mw total = 1.241 w
lucent technologies inc. 149 data sheet june 1999 orca series 3c and 3t fpgas pin information pin descriptions this section describes the pins found on the series 3 fpgas. any pin not described in this table is a user-program- mable i/o. during configuration, the user-programmable i/os are 3-stated with an internal pull-up resistor enabled. if any pin is not used (or not bonded to a package pin), it is also 3-stated with an internal pull-up resistor enabled after configuration. table 67. pin descriptions s y mbol i/o descri p tion dedicated pins v dd positive power suppl y . gnd ground suppl y . v dd 5 5 v tolerant select. v dd 5 pin locations are shown for packa g e compatibilit y with or2txxa devices. connections to 5 v power sources are not used for 5 v tolerant i/os in the or3txxx devices. reset idurin g confi g uration, reset forces the restart of confi g uration and a pull-up is enabled. after confi g uration, reset can be used as a g eneral fpga input or as a direct input, which causes all plc latches/ffs to be as y nchronousl y set/reset. cclk i in the master and as y nchronous peripheral modes, cclk is an output which strobes confi g uration data in. in the slave or s y nchronous peripheral mode, cclk is input s y nchronous with the data on din or d [ 7:0 ] . in microprocessor mode, cclk is used internall y and output for dais y -chain operation. done i o as an input, a low level on done dela y s fpga start-up after confi g uration ( see note ) . as an active-hi g h, open-drain output, a hi g h level on this si g nal indicates that confi g - uration is complete. done has an optional pull-up resistor. prgm i prgm is an active-low input that forces the restart of confi g uration and resets the boundar y -scan circuitr y . this pin alwa y s has an active pull-up. rd_cfg i this pin must be held hi g h durin g device initialization until the init pin g oes hi g h. this pin alwa y s has an active pull-up. durin g confi g uration, rd_cfg is an active-low input that activates the ts_all func- tion and 3-states all of the i/o. after confi g uration, rd_cfg can be selected ( via a bit stream option ) to activate the ts_all function as described above, or, if readback is enabled via a bit stream option, a hi g h-to-low transition on rd_cfg will initiate readback of the confi g uration data, includin g pfu output states, startin g with frame address 0. rd_data/tdo o rd_data/tdo is a dual-function pin. if used for readback, rd_data provides con- fi g uration data out. if used in boundar y scan, tdo is test data out. s p ecial-pur p ose pins m0, m1, m2 i i/o durin g powerup and initialization, m0m2 are used to select the confi g uration mode with their values latched on the risin g ed g e of init ; see table 34 for the confi g - uration modes. durin g confi g uration, a pull-up is enabled. after confi g uration, these pins are user-pro g rammable i/o ( see note ) . note: the fpga states of operation section contains more information on how to control these si g nals durin g start-up. the timin g of done release is controlled b y one set of bit stream options, and the timin g of the simultaneous release of all other confi g uration pins ( and the activation of all user i/os ) is controlled b y a second set of options.
150 lucent technologies inc. data sheet june 1999 orca series 3c and 3t fpgas pin information (continued) table 67. pin descriptions ( continued ) s y mbol i/o descri p tion s p ecial-pur p ose pins ( continued ) m3 i i/o durin g powerup and initialization, m3 is used to select the speed of the internal oscillator dur- in g confi g uration with their values latched on the risin g ed g e of init . when m3 is low, the oscillator fre q uenc y is 10 mhz. when m3 is hi g h, the oscillator is 1.25 mhz. durin g confi g ura- tion, a pull-up is enabled. after confi g uration, this pin is a user-pro g rammable i/o pin ( see note ) . tdi, tck, tms i i/o if boundar y scan is used, these pins are test data in, test clock, and test mode select inputs. if boundar y scan is not selected, all boundar y -scan functions are inhibited once confi g uration is complete. even if boundar y scan is not used, either tck or tms must be held at lo g ic 1 dur- in g confi g uration. each pin has a pull-up enabled durin g confi g uration. after confi g uration, these pins are user-pro g rammable i/o ( see note ) . rdy/rclk/ mpi_ale o o i i/o durin g confi g uration in peripheral mode, rdy/rclk indicates another b y te can be written to the fpga. if a read operation is done when the device is selected, the same status is also available on d7 in as y nchronous peripheral mode. durin g the master parallel confi g uration mode, rclk is a read output si g nal to an external memor y . this output is not normall y used. in i960 microprocessor mode, this pin acts as the address latch enable ( ale ) input. after confi g uration, if the mpi is not used, this pin is a user-pro g rammable i/o pin ( see note ) . hdc o i/o hi g h durin g confi g uration is output hi g h until confi g uration is complete. it is used as a control output, indicatin g that confi g uration is not complete. after confi g uration, this pin is a user-pro g rammable i/o pin ( see note ) . ldc o i/o low durin g confi g uration is output low until confi g uration is complete. it is used as a control out- put, indicatin g that confi g uration is not complete. after confi g uration, this pin is a user-pro g rammable i/o pin ( see note ) . init i/o i/o init is a bidirectional si g nal before and durin g confi g uration. durin g confi g uration, a pull-up is enabled, but an external pull-up resistor is recommended. as an active-low open-drain out- put, init is held low durin g power stabilization and internal clearin g of memor y . as an active- low input, init holds the fpga in the wait-state before the start of confi g uration. after confi g uration, this pin is a user-pro g rammable i/o pin ( see note ) . note: the fpga states of operation section contains more information on how to control these si g nals durin g start-up. the timin g of done release is controlled b y one set of bit stream options, and the timin g of the simultaneous release of all other confi g uration pins ( and the activation of all user i/os ) is controlled b y a second set of options.
lucent technologies inc. 151 data sheet june 1999 orca series 3c and 3t fpgas s p ecial-pur p ose pins ( continued ) cs0 , cs1 i i/o cs0 and cs1 are used in the as y nchronous peripheral, slave parallel, and microprocessor confi g uration modes. the fpga is selected when cs0 is low and cs1 is hi g h. durin g confi g - uration, a pull-up is enabled. after confi g uration, these pins are user-pro g rammable i/o pins ( see note ) . rd / mpi_strb i i i/o rd is used in the as y nchronous peripheral confi g uration mode. a low on rd chan g es d7 into a status output. as a status indication, a hi g h indicates read y , and a low indicates bus y . wr and rd should not be used simultaneousl y . if the y are, the write strobe overrides. this pin is also used as the microprocessor interface ( mpi ) data transfer strobe. for powerpc , it is the transfer start ( ts ) . for i960 , it is the address/data strobe ( ads ) . after confi g uration, if the mpi is not used, this pin is a user-pro g rammable i/o pin ( see note ) . wr i i/o wr is used in the as y nchronous peripheral confi g uration mode. when the fpga is selected, a low on the write strobe, wr , loads the data on d [ 7:0 ] inputs into an internal data buffer. wr and rd should not be used simultaneousl y . if the y are, the write strobe overrides. after confi g uration, this pin is a user-pro g rammable i/o pin ( see note ) . a [ 17:0 ] o i/o durin g master parallel confi g uration mode, a [ 17:0 ] address the confi g uration eprom. in microprocessor interface ( mpi ) mode, man y of the a [ n ] pins have alternate uses as described below. see the special function blocks section for more mpi information. durin g confi g ura- tion, if not in master parallel or an mpi confi g uration mode, these pins are 3-stated with a pull- up enabled. after confi g uration, the pins are user-pro g rammable i/o pins ( see note ) . pin information (continued) table 67. pin descriptions ( continued ) s y mbol i/o descri p tion note: the fpga states of operation section contains more information on how to control these si g nals durin g start-up. the timin g of done release is controlled b y one set of bit stream options, and the timin g of the simultaneous release of all other confi g uration pins ( and the activation of all user i/os ) is controlled b y a second set of options.
152 lucent technologies inc. data sheet june 1999 orca series 3c and 3t fpgas s p ecial-pur p ose pins ( continued ) a11/ mpi_irq o i/o mpi active-low interrupt re q uest output. after confi g uration, if the mpi is not used, this pin is a user-pro g rammable i/o pin ( see note ) . a10/ mpi_bi o i/o powerpc mode mpi burst inhibit output. after confi g uration, if the mpi is not used, this pin is a user-pro g rammable i/o pin ( see note ) . a9/ mpi_ack o i/o in powerpc mode mpi operation, this is the active-hi g h transfer acknowled g e ( ta ) output. for i960 mpi operation, it is the active-low read y /record ( rdyrcv ) output. after confi g uration, if the mpi is not used, this pin is a user-pro g rammable i/o pin ( see note ) . a8/mpi_rw i i/o in powerpc mode mpi operation, this is the active-low write/active-hi g h read control si g nals. for i960 operation, it is the active-hi g h write/active-low read control si g nal. after confi g uration, if the mpi is not used, this pin is a user-pro g rammable i/o pin ( see note ) . a7/mpi_clk i i/o this is the clock used for the s y nchronous mpi interface. for powerpc , it is the clkout si g nal. for i960 , it is the s y stem clock that is chosen for the i960 external bus interface. after confi g uration, if the mpi is not used, this pin is a user-pro g rammable i/o pin ( see note ) . a [ 4:0 ] i i/o for powerpc operation, these are the powerpc address inputs. the address bit mappin g ( in powerpc /fpga notation ) is a [ 31 ] /a [ 0 ] , a [ 30 ] /a [ 1 ] , a [ 29 ] /a [ 2 ] , a [ 28 ] /a [ 3 ] , a [ 27 ] /a [ 4 ] . note that a [ 27 ] /a [ 4 ] is the msb of the address. the a [ 4:2 ] inputs are not used in i960 mpi mode. after confi g uration, if the mpi is not used, this pin is a user-pro g rammable i/o pin ( see note ) . a [ 1:0 ] / mpi_be[1:0] i i/o for i960 operation, mpi_be[1:0] provide the i960 b y te enable si g nals, be[1:0] , that are used as address bits a [ 1:0 ] in i960 b y te-wide operation. after confi g uration, if the mpi is not used, this pin is a user-pro g rammable i/o pin ( see note ) . d [ 7:0 ] i i/o durin g master parallel, peripheral, and slave parallel confi g uration modes, d [ 7:0 ] receive confi g uration data, and each pin has a pull-up enabled. durin g serial confi g uration modes, d0 is the din input. d [ 7:0 ] are also the data pins for powerpc microprocessor mode and the address/data pins for i960 microprocessor mode. after confi g uration, the pins are user-pro g rammable i/o pins ( see note ) . din i i/o durin g slave serial or master serial confi g uration modes, din accepts serial confi g uration data s y nchronous with cclk. durin g parallel confi g uration modes, din is the d0 input. dur- in g confi g uration, a pull-up is enabled. after confi g uration, this pin is a user-pro g rammable i/o pin ( see note ) . dout o i/o durin g confi g uration, dout is the serial data output that can drive the din of dais y -chained slave lca devices. data out on dout chan g es on the fallin g ed g e of cclk. after confi g uration, dout is a user-pro g rammable i/o pin ( see note ) . pin information (continued) table 67. pin descriptions ( continued ) s y mbol i/o descri p tion note: the fpga states of operation section contains more information on how to control these si g nals durin g start-up. the timin g of done release is controlled b y one set of bit stream options, and the timin g of the simultaneous release of all other confi g uration pins ( and the activation of all user i/os ) is controlled b y a second set of options.
lucent technologies inc. 153 data sheet june 1999 orca series 3c and 3t fpgas pin information (continued) package compatibility table 68 provides the number of user i/os available for the orca series 3 fpgas for each available package. each package has six dedicated configuration pins. tables 7075 provide the package pin and pin function for the orca series 3 fpgas and packages. the bond pad name is identified in the pic nomenclature used in the orca foundry design editor. when the number of fpga bond pads exceeds the number of package pins, bond pads are unused. when the number of package pins exceeds the number of bond pads, package pins are left unconnected (no connects). when a package pin is to be left as a no connect for a specific die, it is indicated as a note in the device pad column for the fpga. the tables provide no information on unused pads. table 68 . orca i/os summary *user i/o count includes four expressclk inputs. device 208-pin sqfp/sqpf2 240-pin sqfp/sqfp2 256-pin pbga 352-pin pbga 432-pin ebga 600-pin ebga or3t20 user i/os* 171 192 192 192 v dd /v ss 31 40 26 48 confi g uration 6 6 6 6 unused 0 2 32 106 or3t30 user i/os* 171 192 221 224 v dd /v ss 31 40 26 48 confi g uration 6 6 6 6 unused 0 2 3 74 or3c/t55 user i/os* 171 192 223 288 v dd /v ss 31 42 26 48 confi g uration 6 6 6 6 unused 0 0 1 10 or3c/t80 user i/os* 171 192 298 342 v dd /v ss 31 42 48 84 confi g uration 6 6 6 6 unused 0 0 0 0 or3t125 user i/os* 171 192 298 342 448 v dd /v ss 31 42 48 84 140 confi g uration 6 6 6 6 6 unused 0 0 0 0 6
154 lucent technologies inc. data sheet june 1999 orca series 3c and 3t fpgas pin information ( continued ) compatibility with or2c/txxa series the pinouts shown for the or3cxx and or3txxx devices are consistent with the or2c/txxa series for all devices offered in the same packages. this includes the following pins: v dd , v ss , v dd 5 (or2txxa series only), and all configuration pins. the following restrictions apply: 1. there are two confi g uration modes supported in the or2c/txxa series that are not supported in series 3: mas- ter parallel down and s y nchronous peripheral modes. the series 3 fpgas have two new microprocessor inter- face ( mpi ) confi g uration modes that are unavailable in the or2c/txxa series. 2. there are four pinsone per each device sidethat are user i/o in the or2c/txxa series which can onl y be used as fast dedicated clocks or g lobal inputs in series 3. these pins are also used to drive the expressclk to the i/o ffs on their g iven side of the device. these four middle expressclk pins should not be used to connect to a pro g rammable clock mana g er ( pcm ) . a corner expressclk input should be used instead ( see item 3 below ) . see table 69 for a list of these pins in each packa g e. 3. there are two other pins that are user i/o in both the or2c/txxa and series 3 but also have optional added functionalit y . each of these pins drives the expressclks on two sides of the device. the y also have fast connec- tivit y to the pro g rammable clock mana g er ( pcm ) . see table 69 for a list of these pins in each packa g e. table 69. series 3 ex p ressclk pins pin name/ packa g e 208-pin sqfp/sqfp2 240-pin sqfp/sqfp2 256-pin pbga 352-pin pbga 432-pin ebga 600-pin ebga i-eckl 22 26 k3 n2 r29 u33 i-eckb 80 91 w11 ae14 ah16 am18 i-eckr 131 152 k18 n23 t2 v2 i-eckt 178 207 b11 b14 c15 c17 i/o-seckll 49 56 w1 ab4 ag29 ak34 i/o-seckur 159 184 a19 a25 d5 d5
lucent technologies inc. 155 data sheet june 1999 orca series 3c and 3t fpgas pin information (continued) table 70. or3t20, or3t30, or3c/t55, or3c/t80, and or3t125 208-pin sqfp/sqfp2 pinout pin or3t20 pad or3t30 pad or3c/t55 pad or3c/t80 pad or3t125 pad function 1 v ss v ss v ss v ss v ss v ss 2 v ss v ss v ss v ss v ss v ss 3 pl1d pl1d pl1d pl1d pl1d i/o 4 pl1a pl2d pl2d pl2d pl2d i/o-a0/ mpi_be0 5 pl2d pl4d pl3d pl4d pl4d i/o 6 pl2c pl5d pl3a pl4a pl5d i/o 7 pl2a pl7d pl4a pl5a pl7d i/o-a1/ mpi_be1 8 pl3d pl8a pl5a pl6a pl8a i/o-a2 9 pl3c pl9d pl6d pl7d pl9d i/o 10 pl3b pl9b pl6b pl7b pl9b i/o 11 pl3a pl9a pl6a pl7a pl9a i/o-a3 12 v dd v dd v dd v dd v dd v dd 13 pl4d pl10d pl7d pl8d pl10d i/o 14 pl4c pl10a pl7c pl8a pl10a i/o 15 pl4b pl11d pl7b pl9d pl11d i/o 16 pl4a pl11a pl7a pl9b pl11a i/o-a4 17 pl5d pl12d pl8d pl9a pl12d i/o-a5 18 pl5c pl12a pl8c pl10c pl12a i/o 19 pl5b pl13d pl8b pl10b pl13d i/o 20 pl5a pl13a pl8a pl10a pl13a i/o-a6 21 v ss v ss v ss v ss v ss v ss 22 peckl peckl peckl peckl peckl i-eckl 23 pl6c pl14c pl9c pl11c pl14c i/o 24 pl6b pl14b pl9b pl11b pl14b i/o 25 pl6a pl14a pl9a pl11a pl14a i/o-a7/mpi_clk 26 v dd v dd v dd v dd v dd v dd 27 pl7d pl15d pl10d pl12d pl15d i/o 28 pl7c pl15c pl10c pl12c pl15c i/o 29 pl7b pl15b pl10b pl12b pl15b i/o 30 pl7a pl15a pl10a pl12a pl15a i/o-a8/mpi_rw 31 v ss v ss v ss v ss v ss v ss 32 pl8d pl16d pl11d pl13d pl16d i/o-a9/ mpi_ack 33 pl8c pl16a pl11c pl13b pl16a i/o 34 pl8b pl17d pl11b pl13a pl17d i/o 35 pl8a pl17a pl11a pl14c pl17a i/o-a10/ mpi_bi 36 pl9d pl18d pl12d pl14b pl18d i/o 37 pl9c pl18a pl12c pl15c pl18a i/o 38 pl9b pl19d pl12b pl15b pl19d i/o 39 pl9a pl19a pl12a pl15a pl19a i/o-a11/ mpi_irq pin information (continued) table 70. or3t20, or3t30, or3c/t55, or3c/t80, and or3t125 208-pin sqfp/sqfp2 pinout pin or3t20 pad or3t30 pad or3c/t55 pad or3c/t80 pad or3t125 pad function 1 v ss v ss v ss v ss v ss v ss 2 v ss v ss v ss v ss v ss v ss 3 pl1d pl1d pl1d pl1d pl1d i/o 4 pl1a pl2d pl2d pl2d pl2d i/o-a0/ mpi_be0 5 pl2d pl4d pl3d pl4d pl4d i/o 6 pl2c pl5d pl3a pl4a pl5d i/o 7 pl2a pl7d pl4a pl5a pl7d i/o-a1/ mpi_be1 8 pl3d pl8a pl5a pl6a pl8a i/o-a2 9 pl3c pl9d pl6d pl7d pl9d i/o 10 pl3b pl9b pl6b pl7b pl9b i/o 11 pl3a pl9a pl6a pl7a pl9a i/o-a3 12 v dd v dd v dd v dd v dd v dd 13 pl4d pl10d pl7d pl8d pl10d i/o 14 pl4c pl10a pl7c pl8a pl10a i/o 15 pl4b pl11d pl7b pl9d pl11d i/o 16 pl4a pl11a pl7a pl9b pl11a i/o-a4 17 pl5d pl12d pl8d pl9a pl12d i/o-a5 18 pl5c pl12a pl8c pl10c pl12a i/o 19 pl5b pl13d pl8b pl10b pl13d i/o 20 pl5a pl13a pl8a pl10a pl13a i/o-a6 21 v ss v ss v ss v ss v ss v ss 22 peckl peckl peckl peckl peckl i-eckl 23 pl6c pl14c pl9c pl11c pl14c i/o 24 pl6b pl14b pl9b pl11b pl14b i/o 25 pl6a pl14a pl9a pl11a pl14a i/o-a7/mpi_clk 26 v dd v dd v dd v dd v dd v dd 27 pl7d pl15d pl10d pl12d pl15d i/o 28 pl7c pl15c pl10c pl12c pl15c i/o 29 pl7b pl15b pl10b pl12b pl15b i/o 30 pl7a pl15a pl10a pl12a pl15a i/o-a8/mpi_rw 31 v ss v ss v ss v ss v ss v ss 32 pl8d pl16d pl11d pl13d pl16d i/o-a9/ mpi_ack 33 pl8c pl16a pl11c pl13b pl16a i/o 34 pl8b pl17d pl11b pl13a pl17d i/o 35 pl8a pl17a pl11a pl14c pl17a i/o-a10/ mpi_bi 36 pl9d pl18d pl12d pl14b pl18d i/o 37 pl9c pl18a pl12c pl15c pl18a i/o 38 pl9b pl19d pl12b pl15b pl19d i/o 39 pl9a pl19a pl12a pl15a pl19a i/o-a11/ mpi_irq
156 lucent technologies inc. data sheet june 1999 orca series 3c and 3t fpgas 40 v dd v dd v dd v dd v dd v dd 41 pl10d pl20d pl13d pl16d pl20d i/o-a12 42 pl10c pl20b pl13b pl16b pl20b i/o 43 pl10b pl21d pl14d pl17d pl21d i/o 44 pl10a pl21b pl14b pl17b pl21b i/o-a13 45 pl11d pl22d pl15d pl18d pl22d i/o 46 pl11a pl24a pl16d pl19d pl24a i/o-a14 47 pl12d pl26d pl17d pl20d pl26d i/o 48 pl12c pl27d pl17a pl21d pl27d i/o 49 pl12b pl27a pl18c pl21a pl27a i/o-seckll 50 pl12a pl28a pl18a pl22a pl28a i/o-a15 51 v ss v ss v ss v ss v ss v ss 52 pcclk pcclk pcclk pcclk pcclk cclk 53 v ss v ss v ss v ss v ss v ss 54 v ss v ss v ss v ss v ss v ss 55 pb1a pb1a pb1a pb1a pb1a i/o-a16 56 pb1b pb2a pb1d pb2a pb2a i/o 57 pb1c pb2d pb2a pb2d pb2d i/o 58 pb1d pb3d pb2d pb3d pb3d i/o 59 pb2a pb4d pb3d pb4d pb4d i/o-a17 60 pb2d pb5d pb4d pb5d pb5d i/o 61 pb3a pb6d pb5b pb6b pb6d i/o 62 pb3b pb7d pb5d pb6d pb7d i/o 63 pb3c pb8d pb6b pb7b pb8d i/o 64 pb3d pb9d pb6d pb7d pb9d i/o 65 v dd v dd v dd v dd v dd v dd 66 pb4a pb10a pb7a pb8a pb10a i/o 67 pb4b pb10d pb7b pb8d pb10d i/o 68 pb4c pb11a pb7c pb9a pb11a i/o 69 pb4d pb11d pb7d pb9c pb11d i/o 70 pb5a pb12a pb8a pb9d pb12a i/o 71 pb5b pb12d pb8b pb10a pb12d i/o 72 pb5c pb13a pb8c pb10b pb13a i/o 73 pb5d pb13d pb8d pb10d pb13d i/o 74 v ss v ss v ss v ss v ss v ss 75 pb6a pb14a pb9a pb11a pb14a i/o 76 pb6b pb14b pb9b pb11b pb14b i/o 77 pb6c pb14c pb9c pb11c pb14c i/o 78 pb6d pb14d pb9d pb11d pb14d i/o pin or3t20 pad or3t30 pad or3c/t55 pad or3c/t80 pad or3t125 pad function pin information ( continued ) table 70. or3t20, or3t30, or3c/t55, or3c/t80, and or3t125, 208-pin sqfp/sqfp2 pinout (continued)
lucent technologies inc. 157 data sheet june 1999 orca series 3c and 3t fpgas 79 v ss v ss v ss v ss v ss v ss 80 peckb peckb peckb peckb peckb i-eckb 81 pb7b pb15b pb10b pb12b pb15b i/o 82 pb7c pb15c pb10c pb12c pb15c i/o 83 pb7d pb15d pb10d pb12d pb15d i/o 84 v ss v ss v ss v ss v ss v ss 85 pb8a pb16a pb11a pb13a pb16a i/o 86 pb8b pb16d pb11b pb13b pb16d i/o 87 pb8c pb17a pb11c pb13c pb17a i/o 88 pb8d pb17d pb11d pb14a pb17d i/o 89 pb9a pb18a pb12a pb14b pb18a i/o-hdc 90 pb9b pb18d pb12b pb14d pb18d i/o 91 pb9c pb19a pb12c pb15a pb19a i/o 92 pb9d pb19d pb12d pb15d pb19d i/o 93 v dd v dd v dd v dd v dd v dd 94 pb10a pb20a pb13a pb16a pb20a i/o- ldc 95 pb10b pb21d pb13d pb16d pb21d i/o 96 pb10c pb22a pb14a pb17a pb22a i/o 97 pb10d pb23d pb14d pb17d pb23d i/o 98 pb11a pb24a pb15a pb18a pb24a i/o- init 99 pb11c pb25a pb16a pb19a pb25a i/o 100 pb11d pb26a pb17a pb20a pb26a i/o 101 pb12a pb27d pb18a pb21d pb27d i/o 102 pb12d pb28d pb18d pb22d pb28d i/o 103 v ss v ss v ss v ss v ss v ss 104 pdone pdone pdone pdone pdone done 105 v ss v ss v ss v ss v ss v ss 106 presetn presetn presetn presetn presetn reset 107 pprgmn pprgmn pprgmn pprgmn pprgmn prgm 108 pr12a pr28a pr18a pr22a pr28a i/o-m0 109 pr12d pr27a pr18d pr21a pr27a i/o 110 pr11a pr26a pr17b pr20a pr26a i/o 111 pr11b pr25a pr16a pr19a pr25a i/o 112 pr10a pr22d pr15d pr18d pr22d i/o-m1 113 pr10b pr21a pr14a pr17a pr21a i/o 114 pr10c pr21d pr14d pr17d pr21d i/o 115 pr10d pr20a pr13a pr16a pr20a i/o 116 v dd v dd v dd v dd v dd v dd 117 pr9a pr19a pr12a pr15a pr19a i/o-m2 pin or3t20 pad or3t30 pad or3c/t55 pad or3c/t80 pad or3t125 pad function pin information ( continued ) table 70. or3t20, or3t30, or3c/t55, or3c/t80, and or3t125 208-pin sqfp/sqfp2 pinout (continued)
158 lucent technologies inc. data sheet june 1999 orca series 3c and 3t fpgas 118 pr9b pr19d pr12b pr15d pr19d i/o 119 pr9c pr18a pr12c pr14a pr18a i/o 120 pr9d pr18d pr12d pr14c pr18d i/o 121 pr8a pr17a pr11a pr14d pr17a i/o-m3 122 pr8b pr17d pr11b pr13a pr17d i/o 123 pr8c pr16a pr11c pr13b pr16a i/o 124 pr8d pr16d pr11d pr13d pr16d i/o 125 v ss v ss v ss v ss v ss v ss 126 pr7a pr15a pr10a pr12a pr15a i/o 127 pr7b pr15b pr10b pr12b pr15b i/o 128 pr7c pr15c pr10c pr12c pr15c i/o 129 pr7d pr15d pr10d pr12d pr15d i/o 130 v dd v dd v dd v dd v dd v dd 131 peckr peckr peckr peckr peckr i-eckr 132 pr6b pr14b pr9b pr11b pr14b i/o 133 pr6c pr14c pr9c pr11c pr14c i/o 134 pr6d pr14d pr9d pr11d pr14d i/o 135 v ss v ss v ss v ss v ss v ss 136 pr5a pr13a pr8a pr10a pr13a i/o 137 pr5b pr13d pr8b pr10c pr13d i/o 138 pr5c pr12a pr8c pr10d pr12a i/o 139 pr5d pr12d pr8d pr9b pr12d i/o 140 pr4a pr11a pr7a pr9c pr11a i/o-cs1 141 pr4b pr11d pr7b pr9d pr11d i/o 142 pr4c pr10a pr7c pr8a pr10a i/o 143 pr4d pr10d pr7d pr8d pr10d i/o 144 v dd v dd v dd v dd v dd v dd 145 pr3a pr9a pr6a pr7a pr9a i/o- cs0 146 pr3b pr9b pr6b pr7b pr9b i/o 147 pr3c pr8b pr5b pr6b pr8b i/o 148 pr3d pr8d pr5d pr6d pr8d i/o 149 pr2a pr7a pr4a pr5a pr7a i/o- rd / mpi_strb 150 pr2c pr5a pr4d pr5d pr5a i/o 151 pr2d pr4a pr3a pr4a pr4a i/o 152 pr1a pr3a pr2a pr3a pr3a i/o-wr 153 pr1c pr2a pr2c pr2a pr2a i/o 154 pr1d pr1a pr1a pr1a pr1a i/o 155 v ss v ss v ss v ss v ss v ss 156 prd_cfgn prd_cfgn prd_cfgn prd_cfgn prd_cfgn rd_cfg pin or3t20 pad or3t30 pad or3c/t55 pad or3c/t80 pad or3t125 pad function pin information ( continued ) table 70. or3t20, or3t30, or3c/t55, or3c/t80, and or3t125 208-pin sqfp/sqfp2 pinout (continued)
lucent technologies inc. 159 data sheet june 1999 orca series 3c and 3t fpgas 157 v ss v ss v ss v ss v ss v ss 158 v ss v ss v ss v ss v ss v ss 159 pt12d pt28d pt18d pt22d pt28d i/o-seckur 160 pt12a pt27a pt17d pt21a pt27a i/o-rdy/rclk/mpi_ale 161 pt11d pt25d pt16d pt19d pt25d i/o 162 pt11c pt25a pt16a pt19a pt25a i/o 163 pt11a pt24d pt15d pt18d pt24d i/o-d7 164 pt10d pt23d pt14d pt17d pt23d i/o 165 pt10c pt22d pt14a pt17a pt22d i/o 166 pt10b pt21d pt13d pt16d pt21d i/o 167 pt10a pt20d pt13b pt16b pt20d i/o-d6 168 v dd v dd v dd v dd v dd v dd 169 pt9d pt19d pt12d pt15d pt19d i/o 170 pt9c pt19a pt12c pt15b pt19a i/o 171 pt9b pt18d pt12b pt15a pt18d i/o 172 pt9a pt18a pt12a pt14c pt18a i/o-d5 173 pt8d pt17d pt11d pt14b pt17d i/o 174 pt8c pt17a pt11c pt13d pt17a i/o 175 pt8b pt16d pt11b pt13c pt16d i/o 176 pt8a pt16a pt11a pt13a pt16a i/o-d4 177 v ss v ss v ss v ss v ss v ss 178 peckt peckt peckt peckt peckt i-eckt 179 pt7c pt15c pt10c pt12c pt15c i/o 180 pt7b pt15b pt10b pt12b pt15b i/o 181 pt7a pt15a pt10a pt12a pt15a i/o-d3 182 v ss v ss v ss v ss v ss v ss 183 pt6d pt14d pt9d pt11d pt14d i/o 184 pt6c pt14c pt9c pt11c pt14c i/o 185 pt6b pt14b pt9b pt11b pt14b i/o 186 pt6a pt14a pt9a pt11a pt14a i/o-d2 187 v ss v ss v ss v ss v ss v ss 188 pt5d pt13d pt8d pt10d pt13d i/o-d1 189 pt5c pt13a pt8c pt10b pt13a i/o 190 pt5b pt12d pt8b pt10a pt12d i/o 191 pt5a pt12a pt8a pt9c pt12a i/o-d0/din 192 pt4d pt11d pt7d pt9b pt11d i/o 193 pt4c pt11a pt7c pt8d pt11a i/o 194 pt4b pt10d pt7b pt8c pt10d i/o 195 pt4a pt10a pt7a pt8a pt10a i/o-dout 196 v dd v dd v dd v dd v dd v dd pin or3t20 pad or3t30 pad or3c/t55 pad or3c/t80 pad or3t125 pad function pin information ( continued ) table 70. or3t20, or3t30, or3c/t55, or3c/t80, and or3t125 208-pin sqfp/sqfp2 pinout (continued)
160 lucent technologies inc. data sheet june 1999 orca series 3c and 3t fpgas 197 pt3d pt9d pt6d pt7d pt9d i/o 198 pt3c pt8a pt6a pt7a pt8a i/o 199 pt3b pt7a pt5c pt6c pt7a i/o 200 pt3a pt6a pt5a pt6a pt6a i/o-tdi 201 pt2d pt5a pt4a pt5a pt5a i/o 202 pt2a pt4a pt3a pt4a pt4a i/o-tms 203 pt1d pt3a pt2c pt3a pt3a i/o 204 pt1c pt2a pt2a pt2a pt2a i/o 205 pt1b pt1d pt1d pt1d pt1d i/o 206 pt1a pt1a pt1a pt1a pt1a i/o-tck 207 v ss v ss v ss v ss v ss v ss 208 prd_data prd_data prd_data prd_data prd_data rd_data/tdo pin or3t20 pad or3t30 pad or3c/t55 pad or3c/t80 pad or3t125 pad function pin information ( continued ) table 70. or3t20, or3t30, or3c/t55, or3c/t80, and or3t125 208-pin sqfp/sqfp2 pinout (continued)
lucent technologies inc. 161 data sheet june 1999 orca series 3c and 3t fpgas pin information ( continued ) table 71. or3t20, or3t30, or3c/t55, or3c/t80, and or3t125 240-pin sqfp/sqfp2 pinout pin or3t20 pad or3t30 pad or3c/t55 pad or3c/t80 pad or3t125 pad function 1 v ss v ss v ss v ss v ss v ss 2 v dd v dd v dd v dd v dd v dd 3 pl1d pl1d pl1d pl1d pl1d i/o 4 pl1c pl1b pl1c pl1c pl1c i/o 5pl1bpl1apl1bpl1bpl1b i/o 6 pl1a pl2d pl2d pl2d pl2d i/o-a0/ mpi_be0 7v ss v ss v ss v ss v ss v ss 8 pl2d pl3d pl3d pl4d pl4d i/o 9 pl2c pl3c pl3a pl4a pl5d i/o 10 pl2b pl3b pl4d pl5d pl6d i/o 11 pl2a pl3a pl4a pl5a pl7d i/o-a1/ mpi_be1 12 pl3d pl4d pl5a pl6a pl8a i/o-a2 13 pl3c pl4c pl6d pl7d pl9d i/o 14 pl3b pl4b pl6b pl7b pl9b i/o 15 pl3a pl4a pl6a pl7a pl9a i/o-a3 16 v dd v dd v dd v dd v dd v dd 17 pl4d pl5d pl7d pl8d pl10d i/o 18 pl4c pl5c pl7c pl8a pl10a i/o 19 pl4b pl5b pl7b pl9d pl11d i/o 20 pl4a pl5a pl7a pl9b pl11a i/o-a4 21 pl5d pl6d pl8d pl9a pl12d i/o-a5 22 pl5c pl6c pl8c pl10c pl12a i/o 23 pl5b pl6b pl8b pl10b pl13d i/o 24 pl5a pl6a pl8a pl10a pl13a i/o-a6 25 v ss v ss v ss v ss v ss v ss 26 peckl peckl peckl peckl peckl i-eckl 27 pl6c pl7c pl9c pl11c pl14c i/o 28 pl6b pl7b pl9b pl11b pl14b i/o 29 pl6a pl7a pl9a pl11a pl14a i/o-a7/mpi_clk 30 v dd v dd v dd v dd v dd v dd 31 pl7d pl8d pl10d pl12d pl15d i/o 32 pl7c pl8c pl10c pl12c pl15c i/o 33 pl7b pl8b pl10b pl12b pl15b i/o 34 pl7a pl8a pl10a pl12a pl15a i/o-a8/mpi_rw 35 v ss v ss v ss v ss v ss v ss 36 pl8d pl9d pl11d pl13d pl16d i/o-a9/ mpi_ack 37 pl8c pl9c pl11c pl13b pl16a i/o 38 pl8b pl9b pl11b pl13a pl17d i/o 39 pl8a pl9a pl11a pl14c pl17a i/o-a10/ mpi_bi
162 lucent technologies inc. data sheet june 1999 orca series 3c and 3t fpgas 40 pl9d pl10d pl12d pl14b pl18d i/o 41 pl9c pl10c pl12c pl15c pl18a i/o 42 pl9b pl10b pl12b pl15b pl19d i/o 43 pl9a pl10a pl12a pl15a pl19a i/o-a11/ mpi_irq 44 v dd v dd v dd v dd v dd v dd 45 pl10d pl11d pl13d pl16d pl20d i/o-a12 46 pl10c pl11c pl13b pl16b pl20b i/o 47 pl10b pl11b pl14d pl17d pl21d i/o 48 pl10a pl11a pl14b pl17b pl21b i/o-a13 49 pl11d pl12d pl14a pl17a pl21a i/o 50 pl11c pl12c pl15d pl18d pl22d i/o 51 pl11b pl12b pl15b pl18b pl23d i/o 52 pl11a pl12a pl16d pl19d pl24a i/o-a14 53 v ss v ss v ss v ss v ss v ss 54 pl12d pl13d pl17d pl20d pl26d i/o 55 pl12c pl13a pl17a pl21d pl27d i/o 56 pl12b pl14c pl18c pl21a pl27a i/o-seckll 57 pl12a pl14a pl18a pl22a pl28a i/o-a15 58 v ss v ss v ss v ss v ss v ss 59 pcclk pcclk pcclk pcclk pcclk cclk 60 v dd v dd v dd v dd v dd v dd 61 v ss v ss v ss v ss v ss v ss 62 v ss v ss v ss v ss v ss v ss 63 pb1a pb1a pb1a pb1a pb1a i/o-a16 64 pb1b pb1d pb1d pb2a pb2a i/o 65 pb1c pb2a pb2a pb2d pb2d i/o 66 pb1d pb2d pb2d pb3d pb3d i/o 67 v ss v ss v ss v ss v ss v ss 68 pb2a pb3a pb3d pb4d pb4d i/o-a17 69 pb2b pb3b pb4d pb5d pb5d i/o 70 pb2c pb3c pb5a pb6a pb6a i/o 71 pb2d pb3d pb5b pb6b pb6d i/o 72 pb3a pb4a pb5d pb6d pb7d i/o 73 pb3b pb4b pb6a pb7a pb8a i/o 74 pb3c pb4c pb6b pb7b pb8d i/o 75 pb3d pb4d pb6d pb7d pb9d i/o 76 v dd v dd v dd v dd v dd v dd 77 pb4a pb5a pb7a pb8a pb10a i/o 78 pb4b pb5b pb7b pb8d pb10d i/o pin or3t20 pad or3t30 pad or3c/t55 pad or3c/t80 pad or3t125 pad function pin information ( continued ) table 71. or3t20, or3t30, or3c/t55, or3c/t80, and or3t125 240-pin sqfp/sqfp2 pinout (continued)
lucent technologies inc. 163 data sheet june 1999 orca series 3c and 3t fpgas 79 pb4c pb5c pb7c pb9a pb11a i/o 80 pb4d pb5d pb7d pb9c pb11d i/o 81 pb5a pb6a pb8a pb9d pb12a i/o 82 pb5b pb6b pb8b pb10a pb12d i/o 83 pb5c pb6c pb8c pb10b pb13a i/o 84 pb5d pb6d pb8d pb10d pb13d i/o 85 v ss v ss v ss v ss v ss v ss 86 pb6a pb7a pb9a pb11a pb14a i/o 87 pb6b pb7b pb9b pb11b pb14b i/o 88 pb6c pb7c pb9c pb11c pb14c i/o 89 pb6d pb7d pb9d pb11d pb14d i/o 90 v ss v ss v ss v ss v ss v ss 91 peckb peckb peckb peckb peckb i-eckb 92 pb7b pb8b pb10b pb12b pb15b i/o 93 pb7c pb8c pb10c pb12c pb15c i/o 94 pb7d pb8d pb10d pb12d pb15d i/o 95 v ss v ss v ss v ss v ss v ss 96 pb8a pb9a pb11a pb13a pb16a i/o 97 pb8b pb9b pb11b pb13b pb16d i/o 98 pb8c pb9c pb11c pb13c pb17a i/o 99 pb8d pb9d pb11d pb14a pb17d i/o 100 pb9a pb10a pb12a pb14b pb18a i/o-hdc 101 pb9b pb10b pb12b pb14d pb18d i/o 102 pb9c pb10c pb12c pb15a pb19a i/o 103 pb9d pb10d pb12d pb15d pb19d i/o 104 v dd v dd v dd v dd v dd v dd 105 pb10a pb11a pb13a pb16a pb20a i/o- ldc 106 pb10b pb11d pb13d pb16d pb21d i/o 107 pb10c pb12a pb14a pb17a pb22a i/o 108 pb10d pb12b pb14d pb17d pb23d i/o 109 pb11a pb12c pb15a pb18a pb24a i/o- init 110 pb11b pb12d pb15d pb18d pb24d i/o 111 pb11c pb13a pb16a pb19a pb25a i/o 112 pb11d pb13b pb16d pb19d pb25d i/o 113 v ss v ss v ss v ss v ss 114 pb12a pb13d pb17a pb20a pb26a i/o 115 pb12b pb14a pb17d pb21a pb27a i/o 116 pb12c pb14b pb18a pb21d pb27d i/o 117 pb12d pb14d pb18d pb22d pb28d i/o pin or3t20 pad or3t30 pad or3c/t55 pad or3c/t80 pad or3t125 pad function pin information ( continued ) table 71. or3t20, or3t30, or3c/t55, or3c/t80, and or3t125 240-pin sqfp/sqfp2 pinout (continued)
164 lucent technologies inc. data sheet june 1999 orca series 3c and 3t fpgas 118 v ss v ss v ss v ss v ss v ss 119 pdone pdone pdone pdone pdone done 120 v dd v dd v dd v dd v dd v dd 121 v ss v ss v ss v ss v ss v ss 122 presetn presetn presetn presetn presetn reset 123 pprgmn pprgmn pprgmn pprgmn pprgmn prgm 124 pr12a pr14a pr18a pr22a pr28a i/o-m0 125 pr12b pr14d pr18c pr22d pr28d i/o 126 pr12c pr13a pr18d pr21a pr27a i/o 127 pr12d pr13d pr17b pr20a pr26a i/o 128 v ss v ss v ss v ss v ss v ss 129 pr11a pr12a pr16a pr19a pr25a i/o 130 pr11b pr12b pr16d pr19d pr24a i/o 131 pr11c pr12c pr15a pr18a pr23a i/o 132 pr11d pr12d pr15c pr18c pr23d i/o 133 pr10a pr11a pr15d pr18d pr22d i/o-m1 134 pr10b pr11b pr14a pr17a pr21a i/o 135 pr10c pr11c pr14d pr17d pr21d i/o 136 pr10d pr11d pr13a pr16a pr20a i/o 137 v dd v dd v dd v dd v dd v dd 138 pr9a pr10a pr12a pr15a pr19a i/o-m2 139 pr9b pr10b pr12b pr15d pr19d i/o 140 pr9c pr10c pr12c pr14a pr18a i/o 141 pr9d pr10d pr12d pr14c pr18d i/o 142 pr8a pr9a pr11a pr14d pr17a i/o-m3 143 pr8b pr9b pr11b pr13a pr17d i/o 144 pr8c pr9c pr11c pr13b pr16a i/o 145 pr8d pr9d pr11d pr13d pr16d i/o 146 v ss v ss v ss v ss v ss v ss 147 pr7a pr8a pr10a pr12a pr15a i/o 148 pr7b pr8b pr10b pr12b pr15b i/o 149 pr7c pr8c pr10c pr12c pr15c i/o 150 pr7d pr8d pr10d pr12d pr15d i/o 151 v dd v dd v dd v dd v dd v dd 152 peckr peckr peckr peckr peckr i-eckr 153 pr6b pr7b pr9b pr11b pr14b i/o 154 pr6c pr7c pr9c pr11c pr14c i/o 155 pr6d pr7d pr9d pr11d pr14d i/o 156 v ss v ss v ss v ss v ss v ss pin or3t20 pad or3t30 pad or3c/t55 pad or3c/t80 pad or3t125 pad function pin information ( continued ) table 71. or3t20, or3t30, or3c/t55, or3c/t80, and or3t125 240-pin sqfp/sqfp2 pinout (continued)
lucent technologies inc. 165 data sheet june 1999 orca series 3c and 3t fpgas 157 pr5a pr6a pr8a pr10a pr13a i/o 158 pr5b pr6b pr8b pr10c pr13d i/o 159 pr5c pr6c pr8c pr10d pr12a i/o 160 pr5d pr6d pr8d pr9b pr12d i/o 161 pr4a pr5a pr7a pr9c pr11a i/o-cs1 162 pr4b pr5b pr7b pr9d pr11d i/o 163 pr4c pr5c pr7c pr8a pr10a i/o 164 pr4d pr5d pr7d pr8d pr10d i/o 165 v dd v dd v dd v dd v dd v dd 166 pr3a pr4a pr6a pr7a pr9a i/o- cs0 167 pr3b pr4b pr6b pr7b pr9b i/o 168 pr3c pr4c pr5b pr6b pr8b i/o 169 pr3d pr4d pr5d pr6d pr8d i/o 170 pr2a pr3a pr4a pr5a pr7a i/o- rd / mpi_strb 171 pr2b pr3b pr4b pr5b pr6a i/o 172 pr2c pr3c pr4d pr5d pr5a i/o 173 pr2d pr3d pr3a pr4a pr4a i/o 174 v ss v ss v ss v ss v ss v ss 175 pr1a pr2a pr2a pr3a pr3a i/o- wr 176 pr1b pr2d pr2c pr2a pr2a i/o 177 pr1c pr1a pr1a pr1a pr1a i/o 178 pr1d pr1d pr1d pr1d pr1d i/o 179 v ss v ss v ss v ss v ss v ss 180 prd_cfgn prd_cfgn prd_cfgn prd_cfgn prd_cfgn rd_cfg 181 v ss v ss v ss v ss v ss v ss 182 v dd v dd v dd v dd v dd v dd 183 v ss v ss v ss v ss v ss v ss 184 pt12d pt14d pt18d pt22d pt28d i/o-seckur 185 pt12c pt14c pt18b pt22a pt28a i/o 186 pt12b pt14a pt18a pt21d pt27d i/o 187 pt12a pt13d pt17d pt21a pt27a i/o-rdy/rclk/mpi_ale 188 v ss v ss v ss v ss v ss 189 pt11d pt13b pt16d pt19d pt25d i/o 190 pt11c pt13a pt16c pt19c pt25c i/o 191 pt11b pt12d pt16a pt19a pt25a i/o 192 pt11a pt12c pt15d pt18d pt24d i/o-d7 193 pt10d pt12a pt14d pt17d pt23d i/o 194 pt10c pt11d pt14a pt17a pt22d i/o 195 pt10b pt11c pt13d pt16d pt21d i/o pin or3t20 pad or3t30 pad or3c/t55 pad or3c/t80 pad or3t125 pad function pin information ( continued ) table 71. or3t20, or3t30, or3c/t55, or3c/t80, and or3t125 240-pin sqfp/sqfp2 pinout (continued)
166 lucent technologies inc. data sheet june 1999 orca series 3c and 3t fpgas 196 pt10a pt11b pt13b pt16b pt20d i/o-d6 197 v dd v dd v dd v dd v dd v dd 198 pt9d pt10d pt12d pt15d pt19d i/o 199 pt9c pt10c pt12c pt15b pt19a i/o 200 pt9b pt10b pt12b pt15a pt18d i/o 201 pt9a pt10a pt12a pt14c pt18a i/o-d5 202 pt8d pt9d pt11d pt14b pt17d i/o 203 pt8c pt9c pt11c pt13d pt17a i/o 204 pt8b pt9b pt11b pt13c pt16d i/o 205 pt8a pt9a pt11a pt13a pt16a i/o-d4 206 v ss v ss v ss v ss v ss v ss 207 peckt peckt peckt peckt peckt i-eckt 208 pt7c pt8c pt10c pt12c pt15c i/o 209 pt7b pt8b pt10b pt12b pt15b i/o 210 pt7a pt8a pt10a pt12a pt15a i/o-d3 211 v ss v ss v ss v ss v ss v ss 212 pt6d pt7d pt9d pt11d pt14d i/o 213 pt6c pt7c pt9c pt11c pt14c i/o 214 pt6b pt7b pt9b pt11b pt14b i/o 215 pt6a pt7a pt9a pt11a pt14a i/o-d2 216 v ss v ss v ss v ss v ss v ss 217 pt5d pt6d pt8d pt10d pt13d i/o-d1 218 pt5c pt6c pt8c pt10b pt13a i/o 219 pt5b pt6b pt8b pt10a pt12d i/o 220 pt5a pt6a pt8a pt9c pt12a i/o-d0/din 221 pt4d pt5d pt7d pt9b pt11d i/o 222 pt4c pt5c pt7c pt8d pt11a i/o 223 pt4b pt5b pt7b pt8c pt10d i/o 224 pt4a pt5a pt7a pt8a pt10a i/o-dout 225 v dd v dd v dd v dd v dd v dd 226 pt3d pt4d pt6d pt7d pt9d i/o 227 pt3c pt4c pt6a pt7a pt8a i/o 228 pt3b pt4b pt5c pt6c pt7a i/o 229 pt3a pt4a pt5a pt6a pt6a i/o-tdi 230 pt2d pt3d pt4d pt5d pt5d i/o 231 pt2c pt3c pt4a pt5a pt5a i/o 232 pt2b pt3b pt3d pt4d pt4d i/o 233 pt2a pt3a pt3a pt4a pt4a i/o-tms 234 v ss v ss v ss v ss v ss v ss pin or3t20 pad or3t30 pad or3c/t55 pad or3c/t80 pad or3t125 pad function pin information ( continued ) table 71. or3t20, or3t30, or3c/t55, or3c/t80, and or3t125 240-pin sqfp/sqfp2 pinout (continued)
lucent technologies inc. 167 data sheet june 1999 orca series 3c and 3t fpgas 235 pt1d pt2d pt2c pt3a pt3a i/o 236 pt1c pt2a pt2a pt2a pt2a i/o 237 pt1b pt1d pt1d pt1d pt1d i/o 238 pt1a pt1a pt1a pt1a pt1a i/o-tck 239 v ss v ss v ss v ss v ss v ss 240 prd_data prd_data prd_data prd_data prd_data rd_data/tdo pin or3t20 pad or3t30 pad or3c/t55 pad or3c/t80 pad or3t125 pad function pin information ( continued ) table 71. or3t20, or3t30, or3c/t55, or3c/t80, and or3t125 240-pin sqfp/sqfp2 pinout (continued)
168 168 lucent technologies inc. data sheet june 1999 orca series 3c and 3t fpgas pin or3t20 pad or3t30 pad or3c/t55 pad function b1 v dd v dd v dd v dd c2 pl1d pl1d pl1d i/o d2 pl1c pl1b pl1c i/o d3 pl1b pl1a pl1b i/o e4 pl1a pl2d pl2d i/o-a0/mpi_be0 c1 pl2c pl2c i/o d1 pl2b pl2b i/o e3 pl2a pl2a i/o e2 pl2d pl3d pl3d i/o e1 pl2c pl3c pl3a i/o f3 pl2b pl3b pl4d i/o g4 pl2a pl3a pl4a i/o-a1/mpi_be1 f2 pl5d i/o f1 pl3d pl4d pl5a i/o-a2 g3 pl3c pl4c pl6d i/o g2 pl3b pl4b pl6b i/o g1 pl3a pl4a pl6a i/o-a3 h3 pl4d pl5d pl7d i/o h2 pl4c pl5c pl7c i/o h1 pl4b pl5b pl7b i/o j4 pl4a pl5a pl7a i/o-a4 j3 pl5d pl6d pl8d i/o-a5 j2 pl5c pl6c pl8c i/o j1 pl5b pl6b pl8b i/o k2 pl5a pl6a pl8a i/o-a6 k3 peckl peckl peckl i-eckl k1 pl6c pl7c pl9c i/o l1 pl6b pl7b pl9b i/o l2 pl6a pl7a pl9a i/o-a7/mpi_clk l3 pl7d pl8d pl10d i/o l4 pl7c pl8c pl10c i/o m1 pl7b pl8b pl10b i/o m2 pl7a pl8a pl10a i/o-a8/mpi_rw m3 pl8d pl9d pl11d i/o-a9/mpi_ack m4 pl8c pl9c pl11c i/o n1 pl8b pl9b pl11b i/o n2 pl8a pl9a pl11a i/o-a10/mpi_bi n3 pl9d pl10d pl12d i/o p1 pl9c pl10c pl12c i/o p2 pl9b pl10b pl12b i/o r1 pl9a pl10a pl12a i/o-a11/mpi_irq p3 pl10d pl11d pl13d i/o-a12 r2 pl10c pl11c pl13b i/o t1 pl10b pl11b pl14d i/o p4 pl10a pl11a pl14b i/o-a13 r3 pl11d pl12d pl14a i/o t2 pl11c pl12c pl15d i/o u1 pl11b pl12b pl15b i/o t3 pl11a pl12a pl16d i/o-a14 u2 pl13d pl17d i/o v1 pl12d pl13c pl17c i/o t4 pl12c pl13b pl17b i/o u3 pl13a pl17a i/o v2 pl14d pl18d i/o w1 pl12b pl14c pl18c i/o-seckll v3 pl14b pl18b i/o w2 pl12a pl14a pl18a i/o-a15 y1 pcclk pcclk pcclk cclk w3 nc y2 pb1a pb1a pb1a i/o-a16 w4 pb1c pb1c i/o v4 pb1b pb1d pb1d i/o u5 pb1c pb2a pb2a i/o y3 pb1d pb2b pb2b i/o y4 pb2c pb2c i/o v5 pb2d pb2d i/o w5 pb2a pb3a pb3d i/o-a17 y5 pb2b pb3b pb4d i/o v6 pb2c pb3c pb5a i/o u7 pb2d pb3d pb5b i/o w6 pb3a pb4a pb5d i/o y6 pb3b pb4b pb6a i/o v7 pb3c pb4c pb6b i/o w7 pb3d pb4d pb6d i/o y7 pb4a pb5a pb7a i/o v8 pb4b pb5b pb7b i/o w8 pb4c pb5c pb7c i/o y8 pb4d pb5d pb7d i/o u9 pb5a pb6a pb8a i/o v9 pb5b pb6b pb8b i/o w9 pb5c pb6c pb8c i/o y9 pb5d pb6d pb8d i/o w10 pb6a pb7a pb9a i/o v10 pb6b pb7b pb9b i/o y10 pb6c pb7c pb9c i/o y11 pb6d pb7d pb9d i/o pin or3t20 pad or3t30 pad or3c/t55 pad function pin information ( continued ) table 72. or3t20, or3t30, and or3c/t55 256-pin pbga pinout
lucent technologies inc. 169 data sheet june 1999 orca series 3c and 3t fpgas w11 peckb peckb peckb i-eckb v11 pb7b pb8b pb10b i/o u11 pb7c pb8c pb10c i/o y12 pb7d pb8d pb10d i/o w12 pb8a pb9a pb11a i/o v12 pb8b pb9b pb11b i/o u12 pb8c pb9c pb11c i/o y13 pb8d pb9d pb11d i/o w13 pb9a pb10a pb12a i/o-hdc v13 pb9b pb10b pb12b i/o y14 pb9c pb10c pb12c i/o w14 pb9d pb10d pb12d i/o y15 pb10a pb11a pb13a i/o- ldc v14 pb10b pb11b pb13b i/o w15 pb10c pb11c pb13c i/o y16 pb10d pb11d pb13d i/o u14 pb12a pb14a i/o v15 pb12b pb14d i/o w16 pb11a pb12c pb15a i/o- init y17 pb15d i/o v16 pb12d pb16a i/o w17 pb11b pb13a pb16d i/o y18 pb11c pb13b pb17a i/o u16 pb11d pb13c pb17c i/o v17 pb12a pb13d pb17d i/o w18 pb12b pb14a pb18a i/o y19 pb12c pb14b pb18b i/o v18 pb12d pb14c pb18c i/o w19 pb14d pb18d i/o y20 pdone pdone pdone done w20 presetn presetn presetn reset v19 pprgmn pprgmn pprgmn prgm u19 pr12a pr14a pr18a i/o-m0 u18 pr14c pr18c i/o t17 pr14d pr18d i/o v20 pr13a pr17a i/o u20 pr12b pr13b pr17b i/o t18 pr12c pr13c pr17c i/o t19 pr12d pr13d pr17d i/o t20 pr11a pr12a pr16a i/o r18 pr11b pr12b pr16d i/o p17 pr11c pr12c pr15a i/o pin or3t20 pad or3t30 pad or3c/t55 pad function r19 pr11d pr12d pr15c i/o r20 pr10a pr11a pr15d i/o-m1 p18 pr10b pr11b pr14a i/o p19 pr10c pr11c pr14d i/o p20 pr10d pr11d pr13a i/o n18 pr9a pr10a pr12a i/o-m2 n19 pr9b pr10b pr12b i/o n20 pr9c pr10c pr12c i/o m17 pr9d pr10d pr12d i/o m18 pr8a pr9a pr11a i/o-m3 m19 pr8b pr9b pr11b i/o m20 pr8c pr9c pr11c i/o l19 pr8d pr9d pr11d i/o l18 pr7a pr8a pr10a i/o l20 pr7b pr8b pr10b i/o k20 pr7c pr8c pr10c i/o k19 pr7d pr8d pr10d i/o k18 peckr peckr peckr i-eckr k17 pr6b pr7b pr9b i/o j20 pr6c pr7c pr9c i/o j19 pr6d pr7d pr9d i/o j18 pr5a pr6a pr8a i/o j17 pr5b pr6b pr8b i/o h20 pr5c pr6c pr8c i/o h19 pr5d pr6d pr8d i/o h18 pr4a pr5a pr7a i/o-cs1 g20 pr4b pr5b pr7b i/o g19 pr4c pr5c pr7c i/o f20 pr4d pr5d pr7d i/o g18 pr3a pr4a pr6a i/o- cs0 f19 pr3b pr4b pr6b i/o e20 pr3c pr4c pr5b i/o g17 pr3d pr4d pr5d i/o f18 pr2a pr3a pr4a i/o-rd /mpi_strb e19 pr2b pr3b pr4b i/o d20 pr2c pr3c pr4d i/o e18 pr2d pr3d pr3a i/o d19 pr1a pr2a pr2a i/o- wr c20 pr1b pr2b pr2b i/o e17 pr1c pr2c pr2c i/o d18 pr1d pr2d pr2d i/o c19 pr1a pr1a i/o pin or3t20 pad or3t30 pad or3c/t55 pad function pin information ( continued ) table 72. or3t20, or3t30, and or3c/t55 256-pin pbga pinout ( continued )
170 170 lucent technologies inc. data sheet june 1999 orca series 3c and 3t fpgas b20 pr1b pr1b i/o c18 pr1c pr1c i/o b19 pr1d pr1d i/o a20 prd_cfgn prd_cfgn prd_cfgn rd_cfg a19 pt12d pt14d pt18d i/o-seckur b18 pt14c pt18c i/o b17 pt12c pt14b pt18b i/o c17 pt12b pt14a pt18a i/o d16 pt12a pt13d pt17d i/o-rdy/rclk/mpi_ale a18 pt13c pt17a i/o a17 pt11d pt13b pt16d i/o c16 pt11c pt13a pt16c i/o b16 pt11b pt12d pt16a i/o a16 pt11a pt12c pt15d i/o-d7 c15 pt12b pt15a i/o d14 pt10d pt12a pt14d i/o b15 pt10c pt11d pt14a i/o a15 pt10b pt11c pt13d i/o c14 pt10a pt11b pt13b i/o-d6 b14 pt9d pt11a pt13a i/o a14 pt9c pt10d pt12d i/o c13 pt10c pt12c i/o b13 pt9b pt10b pt12b i/o a13 pt9a pt10a pt12a i/o-d5 d12 pt8d pt9d pt11d i/o c12 pt8c pt9c pt11c i/o b12 pt8b pt9b pt11b i/o a12 pt8a pt9a pt11a i/o-d4 b11 peckt peckt peckt i-eckt c11 pt7c pt8c pt10c i/o a11 pt7b pt8b pt10b i/o a10 pt7a pt8a pt10a i/o-d3 b10 pt6d pt7d pt9d i/o c10 pt6c pt7c pt9c i/o d10 pt6b pt7b pt9b i/o a9 pt6a pt7a pt9a i/o-d2 b9 pt5d pt6d pt8d i/o-d1 c9 pt5c pt6c pt8c i/o d9 pt5b pt6b pt8b i/o a8 pt5a pt6a pt8a i/o-d0/din b8 pt4d pt5d pt7d i/o c8 pt4c pt5c pt7c i/o a7 pt4b pt5b pt7b i/o pin or3t20 pad or3t30 pad or3c/t55 pad function b7 pt4a pt5a pt7a i/o-dout a6 pt3d pt4d pt6d i/o c7 pt3c pt4c pt6a i/o b6 pt3b pt4b pt5c i/o a5 pt3a pt4a pt5a i/o-tdi d7 pt2d pt3d pt4d i/o c6 pt2c pt3c pt4a i/o b5 pt2b pt3b pt3d i/o a4 pt2a pt3a pt3a i/o-tms c5 pt2d pt2d i/o b4 pt1d pt2c pt2c i/o a3 pt1c pt2b pt2b i/o d5 pt1b pt2a pt2a i/o c4 pt1d pt1d i/o b3 pt1c pt1c i/o b2 pt1b pt1b i/o a2 pt1a pt1a pt1a i/o-tck c3 prd_data prd_data prd_data rd_data/tdo a1 v ss v ss v ss v ss d4 v ss v ss v ss v ss d8 v ss v ss v ss v ss d13 v ss v ss v ss v ss d17 v ss v ss v ss v ss h4 v ss v ss v ss v ss h17 v ss v ss v ss v ss n4 v ss v ss v ss v ss n17 v ss v ss v ss v ss u4 v ss v ss v ss v ss u8 v ss v ss v ss v ss u13 v ss v ss v ss v ss u17 v ss v ss v ss v ss j9 v ss v ss v ss v ss * j10 v ss v ss v ss v ss * j11 v ss v ss v ss v ss * j12 v ss v ss v ss v ss * k9 v ss v ss v ss v ss * k10 v ss v ss v ss v ss * k11 v ss v ss v ss v ss * k12 v ss v ss v ss v ss * l9 v ss v ss v ss v ss * l10 v ss v ss v ss v ss * l11 v ss v ss v ss v ss * l12 v ss v ss v ss v ss * pin or3t20 pad or3t30 pad or3c/t55 pad function pin information ( continued ) table 72. or3t20, or3t30, and or3c/t55 256-pin pbga pinout ( continued )
lucent technologies inc. 171 data sheet june 1999 orca series 3c and 3t fpgas m9 v ss v ss v ss v ss * m10 v ss v ss v ss v ss * m11 v ss v ss v ss v ss * m12 v ss v ss v ss v ss * d6 v dd v dd v dd v dd d11 v dd v dd v dd v dd d15 v dd v dd v dd v dd f4 v dd v dd v dd v dd pin or3t20 pad or3t30 pad or3c/t55 pad function f17 v dd v dd v dd v dd k4 v dd v dd v dd v dd l17 v dd v dd v dd v dd r4 v dd v dd v dd v dd r17 v dd v dd v dd v dd u6 v dd v dd v dd v dd u10 v dd v dd v dd v dd u15 v dd v dd v dd v dd pin or3t20 pad or3t30 pad or3c/t55 pad function pin information ( continued ) table 72. or3t20, or3t30, and or3c/t55 256-pin pbga pinout ( continued ) * thermally enhanced connection.
172 lucent technologies inc. data sheet june 1999 orca series 3c and 3t fpgas pin information ( continued ) table 73. or3t20, or3t30, or3c/t55, or3c/t80, and or3t125 352-pin pbga pinout pin or3t20 pad or3t30 pad or3c/t55 pad or3c/t80 pad or3t125 pad function b1 pl1d pl1d pl1d pl1d pl1d i/o c2 pl1c pl1c pl1c pl1c i/o c1 pl1c pl1b pl1b pl1b pl1b i/o d2 pl1b pl1a pl1a pl1a pl1a i/o d3 pl1a pl2d pl2d pl2d pl2d i/o-a0/ mpi_be0 d1 pl2c pl2c pl2a pl2a i/o e2 pl2b pl2b pl3d pl3d i/o e4 pl3b pl3b i/o e3 pl2a pl2a pl3a pl3a i/o e1 pl2d pl3d pl3d pl4d pl4d i/o f2 pl3c pl4c pl4c i/o g4 pl2c pl3c pl3b pl4b pl4b i/o f3 pl3a pl4a pl5d i/o f1 pl2b pl3b pl4d pl5d pl6d i/o g2 pl4c pl5c pl6c i/o g1 pl4b pl5b pl6b i/o g3 pl2a pl3a pl4a pl5a pl7d i/o-a1/ mpi_be1 h2 pl5d pl6d pl8d i/o j4 pl5c pl6c pl8c i/o h1 pl5b pl6b pl8b i/o h3 pl3d pl4d pl5a pl6a pl8a i/o-a2 j2 pl6d pl7d pl9d i/o j1 pl3c pl4c pl6c pl7c pl9c i/o k2 pl3b pl4b pl6b pl7b pl9b i/o j3 pl3a pl4a pl6a pl7a pl9a i/o-a3 k1 pl4d pl5d pl7d pl8d pl10d i/o k4 pl4c pl5c pl7c pl8a pl10a i/o l2 pl4b pl5b pl7b pl9d pl11d i/o k3 pl4a pl5a pl7a pl9b pl11a i/o-a4 l1 pl5d pl6d pl8d pl9a pl12d i/o-a5 m2 pl5c pl6c pl8c pl10c pl12a i/o m1 pl5b pl6b pl8b pl10b pl13d i/o l3 pl5a pl6a pl8a pl10a pl13a i/o-a6 n2 peckl peckl peckl peckl peckl i-eckl m4 pl6c pl7c pl9c pl11c pl14c i/o n1 pl6b pl7b pl9b pl11b pl14b i/o m3 pl6a pl7a pl9a pl11a pl14a i/o-a7/mpi_clk p2 pl7d pl8d pl10d pl12d pl15d i/o p4 pl7c pl8c pl10c pl12c pl15c i/o p1 pl7b pl8b pl10b pl12b pl15b i/o n3 pl7a pl8a pl10a pl12a pl15a i/o-a8/mpi_rw r2 pl8d pl9d pl11d pl13d pl16d i/o-a9/ mpi_ack
lucent technologies inc. 173 data sheet june 1999 orca series 3c and 3t fpgas p3 pl8c pl9c pl11c pl13b pl16a i/o r1 pl8b pl9b pl11b pl13a pl17d i/o t2 pl8a pl9a pl11a pl14c pl17a i/o-a10/ mpi_bi r3 pl9d pl10d pl12d pl14b pl18d i/o t1 pl9c pl10c pl12c pl15c pl18a i/o r4 pl9b pl10b pl12b pl15b pl19d i/o u2 pl9a pl10a pl12a pl15a pl19a i/o-a11/ mpi_irq t3 pl10d pl11d pl13d pl16d pl20d i/o-a12 u1 pl13c pl16c pl20c i/o u4 pl10c pl11c pl13b pl16b pl20b i/o v2 pl13a pl16a pl20a i/o u3 pl10b pl11b pl14d pl17d pl21d i/o v1 pl14c pl17c pl21c i/o w2 pl10a pl11a pl14b pl17b pl21b i/o-a13 w1 pl14a pl17a pl21a i/o v3 pl11d pl12d pl15d pl18d pl22d i/o y2 pl11c pl12c pl15c pl18c pl22c i/o w4 pl11b pl12b pl15b pl18b pl23d i/o y1 pl15a pl18a pl24d i/o w3 pl11a pl12a pl16d pl19d pl24a i/o-a14 aa2 pl16c pl19c pl25c i/o y4 pl16b pl19b pl25b i/o aa1 pl16a pl19a pl25a i/o y3 pl13d pl17d pl20d pl26d i/o ab2 pl12d pl13c pl17c pl20c pl26c i/o ab1 pl12c pl13b pl17b pl20a pl26a i/o aa3 pl13a pl17a pl21d pl27d i/o ac2 pl14d pl18d pl21c pl27c i/o ab4 pl12b pl14c pl18c pl21a pl27a i/o-seckll ac1 pl14b pl18b pl22d pl28d i/o ab3 pl22c pl28c i/o ad2 pl22b pl28b i/o ac3 pl12a pl14a pl18a pl22a pl28a i/o-a15 ad1 pcclk pcclk pcclk pcclk pcclk cclk af2 pb1a pb1a pb1a pb1a pb1a i/o-a16 ae3 pb1b pb1b i/o af3 pb1b pb1b pb1c pb1c i/o ae4 pb1c pb1c pb1d pb1d i/o ad4 pb1b pb1d pb1d pb2a pb2a i/o af4 pb1c pb2a pb2a pb2d pb2d i/o ae5 pb2b pb3a pb3a i/o ac5 pb1d pb2b pb2c pb3c pb3c i/o ad5 pb2d pb3d pb3d i/o pin or3t20 pad or3t30 pad or3c/t55 pad or3c/t80 pad or3t125 pad function pin information ( continued ) table 73. or3t20, or3t30, or3c/t55, or3c/t80, and or3t125 352-pin pbga pinout ( continued )
174 lucent technologies inc. data sheet june 1999 orca series 3c and 3t fpgas af5 pb2c pb3a pb4a pb4a i/o ae6 pb2d pb3b pb4b pb4b i/o ac7 pb3c pb4c pb4c i/o ad6 pb2a pb3a pb3d pb4d pb4d i/o-a17 af6 pb4a pb5a pb5a i/o ae7 pb4b pb5b pb5b i/o af7 pb4c pb5c pb5c i/o ad7 pb4d pb5d pb5d i/o ae8 pb5a pb6a pb6a i/o ac9 pb2b pb3b pb5b pb6b pb6d i/o af8 pb2c pb3c pb5c pb6c pb7a i/o ad8 pb2d pb3d pb5d pb6d pb7d i/o ae9 pb3a pb4a pb6a pb7a pb8a i/o af9 pb3b pb4b pb6b pb7b pb8d i/o ae10 pb3c pb4c pb6c pb7c pb9a i/o ad9 pb3d pb4d pb6d pb7d pb9d i/o af10 pb4a pb5a pb7a pb8a pb10a i/o ac10 pb4b pb5b pb7b pb8d pb10d i/o ae11 pb4c pb5c pb7c pb9a pb11a i/o ad10 pb4d pb5d pb7d pb9c pb11d i/o af11 pb5a pb6a pb8a pb9d pb12a i/o ae12 pb5b pb6b pb8b pb10a pb12d i/o af12 pb5c pb6c pb8c pb10b pb13a i/o ad11 pb5d pb6d pb8d pb10d pb13d i/o ae13 pb6a pb7a pb9a pb11a pb14a i/o ac12 pb6b pb7b pb9b pb11b pb14b i/o af13 pb6c pb7c pb9c pb11c pb14c i/o ad12 pb6d pb7d pb9d pb11d pb14d i/o ae14 peckb peckb peckb peckb peckb i-eckb ac14 pb7b pb8b pb10b pb12b pb15b i/o af14 pb7c pb8c pb10c pb12c pb15c i/o ad13 pb7d pb8d pb10d pb12d pb15d i/o ae15 pb8a pb9a pb11a pb13a pb16a i/o ad14 pb8b pb9b pb11b pb13b pb16d i/o af15 pb8c pb9c pb11c pb13c pb17a i/o ae16 pb8d pb9d pb11d pb14a pb17d i/o ad15 pb9a pb10a pb12a pb14b pb18a i/o-hdc af16 pb9b pb10b pb12b pb14d pb18d i/o ac15 pb9c pb10c pb12c pb15a pb19a i/o ae17 pb9d pb10d pb12d pb15d pb19d i/o ad16 pb10a pb11a pb13a pb16a pb20a i/o- ldc af17 pb13b pb16b pb20d i/o pin or3t20 pad or3t30 pad or3c/t55 pad or3c/t80 pad or3t125 pad function pin information ( continued ) table 73. or3t20, or3t30, or3c/t55, or3c/t80, and or3t125 352-pin pbga pinout ( continued )
lucent technologies inc. 175 data sheet june 1999 orca series 3c and 3t fpgas ac17 pb10b pb11b pb13c pb16c pb21a i/o ae18 pb10c pb11c pb13d pb16d pb21d i/o ad17 pb10d pb11d pb14a pb17a pb22a i/o af18 pb12a pb14b pb17b pb23a i/o ae19 pb14c pb17c pb23c i/o af19 pb12b pb14d pb17d pb23d i/o ad18 pb11a pb12c pb15a pb18a pb24a i/o- init ae20 pb15b pb18b pb24b i/o ac19 pb15c pb18c pb24c i/o af20 pb15d pb18d pb24d i/o ad19 pb12d pb16a pb19a pb25a i/o ae21 pb16b pb19b pb25b i/o ac20 pb16c pb19c pb25c i/o af21 pb11b pb13a pb16d pb19d pb25d i/o ad20 pb11c pb13b pb17a pb20a pb26a i/o ae22 pb11d pb13c pb17b pb20b pb26b i/o af22 pb12a pb13d pb17c pb20d pb26d i/o ad21 pb12b pb14a pb17d pb21a pb27a i/o ae23 pb21b pb27b i/o ac22 pb12c pb14b pb18a pb21d pb27d i/o af23 pb12d pb14c pb18b pb22a pb28a i/o ad22 pb14d pb18c pb22b pb28b i/o ae24 pb22c pb28c i/o ad23 pb18d pb22d pb28d i/o af24 pdone pdone pdone pdone pdone done ae26 presetn presetn presetn presetn presetn reset ad25 pprgmn pprgmn pprgmn pprgmn pprgmn prgm ad26 pr12a pr14a pr18a pr22a pr28a i/o-m0 ac25 pr14b pr18b pr22c pr28c i/o ac24 pr14c pr18c pr22d pr28d i/o ac26 pr14d pr18d pr21a pr27a i/o ab25 pr13a pr17a pr21d pr27d i/o ab23 pr12b pr13b pr17b pr20a pr26a i/o ab24 pr12c pr13c pr17c pr20b pr26b i/o ab26 pr12d pr13d pr17d pr20d pr26d i/o aa25 pr11a pr12a pr16a pr19a pr25a i/o y23 pr16b pr19b pr25b i/o aa24 pr11b pr12b pr16c pr19c pr25c i/o aa26 pr16d pr19d pr24a i/o y25 pr11c pr12c pr15a pr18a pr23a i/o y26 pr15b pr18b pr23b i/o y24 pr11d pr12d pr15c pr18c pr23d i/o pin or3t20 pad or3t30 pad or3c/t55 pad or3c/t80 pad or3t125 pad function pin information ( continued ) table 73. or3t20, or3t30, or3c/t55, or3c/t80, and or3t125 352-pin pbga pinout ( continued )
176 lucent technologies inc. data sheet june 1999 orca series 3c and 3t fpgas w25 pr10a pr11a pr15d pr18d pr22d i/o-m1 v23 pr10b pr11b pr14a pr17a pr21a i/o w26 pr14b pr17b pr21b i/o w24 pr14c pr17c pr21c i/o v25 pr10c pr11c pr14d pr17d pr21d i/o v26 pr10d pr11d pr13a pr16a pr20a i/o u25 pr13b pr16b pr20b i/o v24 pr13c pr16c pr20c i/o u26 pr13d pr16d pr20d i/o u23 pr9a pr10a pr12a pr15a pr19a i/o-m2 t25 pr9b pr10b pr12b pr15d pr19d i/o u24 pr9c pr10c pr12c pr14a pr18a i/o t26 pr9d pr10d pr12d pr14c pr18d i/o r25 pr8a pr9a pr11a pr14d pr17a i/o-m3 r26 pr8b pr9b pr11b pr13a pr17d i/o t24 pr8c pr9c pr11c pr13b pr16a i/o p25 pr8d pr9d pr11d pr13d pr16d i/o r23 pr7a pr8a pr10a pr12a pr15a i/o p26 pr7b pr8b pr10b pr12b pr15b i/o r24 pr7c pr8c pr10c pr12c pr15c i/o n25 pr7d pr8d pr10d pr12d pr15d i/o n23 peckr peckr peckr peckr peckr i-eckr n26 pr6b pr7b pr9b pr11b pr14b i/o p24 pr6c pr7c pr9c pr11c pr14c i/o m25 pr6d pr7d pr9d pr11d pr14d i/o n24 pr5a pr6a pr8a pr10a pr13a i/o m26 pr5b pr6b pr8b pr10c pr13d i/o l25 pr5c pr6c pr8c pr10d pr12a i/o m24 pr5d pr6d pr8d pr9b pr12d i/o l26 pr4a pr5a pr7a pr9c pr11a i/o-cs1 m23 pr4b pr5b pr7b pr9d pr11d i/o k25 pr4c pr5c pr7c pr8a pr10a i/o l24 pr4d pr5d pr7d pr8d pr10d i/o k26 pr3a pr4a pr6a pr7a pr9a i/o- cs0 k23 pr6b pr7b pr9b i/o j25 pr3b pr4b pr6c pr7c pr9c i/o k24 pr6d pr7d pr9d i/o j26 pr3c pr4c pr5a pr6a pr8a i/o h25 pr5b pr6b pr8b i/o h26 pr3d pr4d pr5c pr6c pr8c i/o j24 pr5d pr6d pr8d i/o g25 pr2a pr3a pr4a pr5a pr7a i/o- rd / mpi_strb pin or3t20 pad or3t30 pad or3c/t55 pad or3c/t80 pad or3t125 pad function pin information ( continued ) table 73. or3t20, or3t30, or3c/t55, or3c/t80, and or3t125 352-pin pbga pinout ( continued )
lucent technologies inc. 177 data sheet june 1999 orca series 3c and 3t fpgas h23 pr2b pr3b pr4b pr5b pr6a i/o g26 pr4c pr5c pr6c i/o h24 pr2c pr3c pr4d pr5d pr5a i/o f25 pr2d pr3d pr3a pr4a pr4a i/o g23 pr3b pr4b pr4b i/o f26 pr3c pr4c pr4c i/o g24 pr3d pr4d pr4d i/o e25 pr1a pr2a pr2a pr3a pr3a i/o- wr e26 pr1b pr2b pr2b pr3b pr3b i/o f24pr3dpr3di/o d25 pr1c pr2c pr2c pr2a pr2a i/o e23 pr1d pr2d pr2d pr2d pr2d i/o d26 pr1a pr1a pr1a pr1a i/o e24 pr1b pr1b pr1b pr1b i/o c25 pr1c pr1c pr1c pr1c i/o d24 pr1d pr1d pr1d pr1d i/o c26 prd_cfgn prd_cfgn prd_cfgn prd_cfgn prd_cfgn rd_cfg a25 pt12d pt14d pt18d pt22d pt28d i/o-seckur b24 pt14c pt18c pt22c pt28c i/o a24pt22bpt28bi/o b23 pt12c pt14b pt18b pt22a pt28a i/o c23 pt12b pt14a pt18a pt21d pt27d i/o a23 pt12a pt13d pt17d pt21a pt27a i/o-rdy/rclk/ mpi_ale b22 pt13c pt17c pt20d pt26d i/o d22 pt11d pt13b pt17b pt20c pt26c i/o c22 pt11c pt13a pt17a pt20a pt26a i/o a22 pt11b pt12d pt16d pt19d pt25d i/o b21 pt16c pt19c pt25c i/o d20 pt16b pt19b pt25b i/o c21 pt16a pt19a pt25a i/o a21 pt11a pt12c pt15d pt18d pt24d i/o-d7 b20 pt15c pt18c pt24c i/o a20 pt12b pt15b pt18b pt24b i/o c20 pt15a pt18a pt24a i/o b19 pt10d pt12a pt14d pt17d pt23d i/o d18 pt14c pt17c pt23c i/o a19 pt10c pt11d pt14b pt17b pt23b i/o c19 pt14a pt17a pt22d i/o b18 pt10b pt11c pt13d pt16d pt21d i/o a18 pt13c pt16c pt21a i/o b17 pt10a pt11b pt13b pt16b pt20d i/o-d6 pin or3t20 pad or3t30 pad or3c/t55 pad or3c/t80 pad or3t125 pad function pin information ( continued ) table 73. or3t20, or3t30, or3c/t55, or3c/t80, and or3t125 352-pin pbga pinout ( continued )
178 lucent technologies inc. data sheet june 1999 orca series 3c and 3t fpgas c18 pt9d pt11a pt13a pt16a pt20a i/o a17 pt9c pt10d pt12d pt15d pt19d i/o d17 pt10c pt12c pt15b pt19a i/o b16 pt9b pt10b pt12b pt15a pt18d i/o c17 pt9a pt10a pt12a pt14c pt18a i/o-d5 a16 pt8d pt9d pt11d pt14b pt17d i/o b15 pt8c pt9c pt11c pt13d pt17a i/o a15 pt8b pt9b pt11b pt13c pt16d i/o c16 pt8a pt9a pt11a pt13a pt16a i/o-d4 b14 peckt peckt peckt peckt peckt i-eckt d15 pt7c pt8c pt10c pt12c pt15c i/o a14 pt7b pt8b pt10b pt12b pt15b i/o c15 pt7a pt8a pt10a pt12a pt15a i/o-d3 b13pt6dpt7dpt9dpt11dpt14d i/o d13pt6cpt7cpt9cpt11cpt14c i/o a13 pt6b pt7b pt9b pt11b pt14b i/o c14 pt6a pt7a pt9a pt11a pt14a i/o-d2 b12pt5dpt6dpt8dpt10dpt13d i/o-d1 c13 pt5c pt6c pt8c pt10b pt13a i/o a12 pt5b pt6b pt8b pt10a pt12d i/o b11 pt5a pt6a pt8a pt9c pt12a i/o-d0/din c12 pt4d pt5d pt7d pt9b pt11d i/o a11pt4cpt5cpt7cpt8dpt11a i/o d12 pt4b pt5b pt7b pt8c pt10d i/o b10 pt4a pt5a pt7a pt8a pt10a i/o-dout c11 pt3d pt4d pt6d pt7d pt9d i/o a10 pt6c pt7c pt9a i/o d10 pt6b pt7b pt8d i/o b9 pt3c pt4c pt6a pt7a pt8a i/o c10 pt3b pt4b pt5d pt6d pt7d i/o a9 pt5c pt6c pt7a i/o b8 pt5b pt6b pt6d i/o a8 pt3a pt4a pt5a pt6a pt6a i/o-tdi c9 pt4d pt5d pt5d i/o b7 pt2d pt3d pt4c pt5c pt5c i/o d8 pt4b pt5b pt5b i/o a7 pt2c pt3c pt4a pt5a pt5a i/o c8 pt3d pt4d pt4d i/o b6 pt2b pt3b pt3c pt4c pt4c i/o d7 pt3b pt4b pt4b i/o a6 pt2a pt3a pt3a pt4a pt4a i/o-tms c7 pt2d pt2d pt3d pt3d i/o pin or3t20 pad or3t30 pad or3c/t55 pad or3c/t80 pad or3t125 pad function pin information ( continued ) table 73. or3t20, or3t30, or3c/t55, or3c/t80, and or3t125 352-pin pbga pinout ( continued )
lucent technologies inc. 179 data sheet june 1999 orca series 3c and 3t fpgas b5 pt1d pt2c pt2c pt3a pt3a i/o a5 pt1c pt2b pt2b pt2d pt2d i/o c6 pt2c pt2c i/o b4 pt2b pt2b i/o d5 pt1b pt2a pt2a pt2a pt2a i/o a4 pt1d pt1d pt1d pt1d i/o c5 pt1c pt1c pt1c pt1c i/o b3 pt1b pt1b pt1b pt1b i/o c4 pt1a pt1a pt1a pt1a pt1a i/o-tck a3 prd_data prd_data prd_data prd_data prd_data rd_data/tdo a1 v ss v ss v ss v ss v ss v ss a2 v ss v ss v ss v ss v ss v ss a26 v ss v ss v ss v ss v ss v ss ac13 v ss v ss v ss v ss v ss v ss ac18 v ss v ss v ss v ss v ss v ss ac23 v ss v ss v ss v ss v ss v ss ac4 v ss v ss v ss v ss v ss v ss ac8 v ss v ss v ss v ss v ss v ss ad24 v ss v ss v ss v ss v ss v ss ad3 v ss v ss v ss v ss v ss v ss ae1 v ss v ss v ss v ss v ss v ss ae2 v ss v ss v ss v ss v ss v ss ae25 v ss v ss v ss v ss v ss v ss af1 v ss v ss v ss v ss v ss v ss af25 v ss v ss v ss v ss v ss v ss af26 v ss v ss v ss v ss v ss v ss b2 v ss v ss v ss v ss v ss v ss b25 v ss v ss v ss v ss v ss v ss b26 v ss v ss v ss v ss v ss v ss c24 v ss v ss v ss v ss v ss v ss c3 v ss v ss v ss v ss v ss v ss d14 v ss v ss v ss v ss v ss v ss d19 v ss v ss v ss v ss v ss v ss d23 v ss v ss v ss v ss v ss v ss d4 v ss v ss v ss v ss v ss v ss d9 v ss v ss v ss v ss v ss v ss h4 v ss v ss v ss v ss v ss v ss j23 v ss v ss v ss v ss v ss v ss n4 v ss v ss v ss v ss v ss v ss p23 v ss v ss v ss v ss v ss v ss v4 v ss v ss v ss v ss v ss v ss w23 v ss v ss v ss v ss v ss v ss pin or3t20 pad or3t30 pad or3c/t55 pad or3c/t80 pad or3t125 pad function pin information ( continued ) table 73. or3t20, or3t30, or3c/t55, or3c/t80, and or3t125 352-pin pbga pinout ( continued )
180 lucent technologies inc. data sheet june 1999 orca series 3c and 3t fpgas l11 v ss v ss v ss v ss v ss v ss * l12 v ss v ss v ss v ss v ss v ss * l13 v ss v ss v ss v ss v ss v ss * l14 v ss v ss v ss v ss v ss v ss * l15 v ss v ss v ss v ss v ss v ss * l16 v ss v ss v ss v ss v ss v ss * m11 v ss v ss v ss v ss v ss v ss * m12 v ss v ss v ss v ss v ss v ss * m13 v ss v ss v ss v ss v ss v ss * m14 v ss v ss v ss v ss v ss v ss * m15 v ss v ss v ss v ss v ss v ss * m16 v ss v ss v ss v ss v ss v ss * n11 v ss v ss v ss v ss v ss v ss * n12 v ss v ss v ss v ss v ss v ss * n13 v ss v ss v ss v ss v ss v ss * n14 v ss v ss v ss v ss v ss v ss * n15 v ss v ss v ss v ss v ss v ss * n16 v ss v ss v ss v ss v ss v ss * p11 v ss v ss v ss v ss v ss v ss * p12 v ss v ss v ss v ss v ss v ss * p13 v ss v ss v ss v ss v ss v ss * p14 v ss v ss v ss v ss v ss v ss * p15 v ss v ss v ss v ss v ss v ss * p16 v ss v ss v ss v ss v ss v ss * r11 v ss v ss v ss v ss v ss v ss * r12 v ss v ss v ss v ss v ss v ss * r13 v ss v ss v ss v ss v ss v ss * r14 v ss v ss v ss v ss v ss v ss * r15 v ss v ss v ss v ss v ss v ss * r16 v ss v ss v ss v ss v ss v ss * t11 v ss v ss v ss v ss v ss v ss * t12 v ss v ss v ss v ss v ss v ss * t13 v ss v ss v ss v ss v ss v ss * t14 v ss v ss v ss v ss v ss v ss * t15 v ss v ss v ss v ss v ss v ss * t16 v ss v ss v ss v ss v ss v ss * aa23 v dd v dd v dd v dd v dd v dd aa4 v dd v dd v dd v dd v dd v dd ac11 v dd v dd v dd v dd v dd v dd ac16 v dd v dd v dd v dd v dd v dd ac21 v dd v dd v dd v dd v dd v dd ac6 v dd v dd v dd v dd v dd v dd pin or3t20 pad or3t30 pad or3c/t55 pad or3c/t80 pad or3t125 pad function pin information ( continued ) table 73. or3t20, or3t30, or3c/t55, or3c/t80, and or3t125 352-pin pbga pinout ( continued )
lucent technologies inc. 181 data sheet june 1999 orca series 3c and 3t fpgas *thermall y enhanced connection. d11 v dd v dd v dd v dd v dd v dd d16 v dd v dd v dd v dd v dd v dd d21 v dd v dd v dd v dd v dd v dd d6 v dd v dd v dd v dd v dd v dd f23 v dd v dd v dd v dd v dd v dd f4 v dd v dd v dd v dd v dd v dd l23 v dd v dd v dd v dd v dd v dd l4 v dd v dd v dd v dd v dd v dd t23 v dd v dd v dd v dd v dd v dd t4 v dd v dd v dd v dd v dd v dd pin or3t20 pad or3t30 pad or3c/t55 pad or3c/t80 pad or3t125 pad function pin information ( continued ) table 73. or3t20, or3t30, or3c/t55, or3c/t80, and or3t125 352-pin pbga pinout ( continued )
182 182 lucent technologies inc. data sheet june 1999 orca series 3c and 3t fpgas pin or3c/t80 pad or3t125 pad function e4 prd_cfgn prd_cfgn rd_cfg d3 pr1d pr1d i/o d2 pr1c pr1c i/o d1 pr1b pr1b i/o f4 pr1a pr1a i/o e3 pr2d pr2d i/o e2 pr2c pr2c i/o e1 pr2b pr2b i/o f3 pr2a pr2a i/o f2 pr3d pr3d i/o f1 pr3c pr3c i/o h4 pr3b pr3b i/o g3 pr3a pr3a i/o- wr g2 pr4d pr4d i/o g1 pr4c pr4c i/o j4 pr4b pr4b i/o h3 pr4a pr4a i/o h2 pr5d pr5a i/o j3 pr5c pr6c i/o k4 pr5b pr6a i/o j2 pr5a pr7a i/o- rd / mpi_strb j1 pr6d pr8d i/o k3 pr6c pr8c i/o k2 pr6b pr8b i/o k1 pr6a pr8a i/o l3 pr7d pr9d i/o m4 pr7c pr9c i/o l2 pr7b pr9b i/o l1 pr7a pr9a i/o- cs0 m3 pr8d pr10d i/o n4 pr8a pr10a i/o m2 pr9d pr11d i/o n3 pr9c pr11a i/o-cs1 n2 pr9b pr12d i/o p4 pr9a pr12c i/o n1 pr10d pr12a i/o p3 pr10c pr13d i/o p2 pr10b pr13c i/o p1 pr10a pr13a i/o r3 pr11d pr14d i/o r2 pr11c pr14c i/o r1 pr11b pr14b i/o t2 peckr peckr i-eckr t4 pr12d pr15d i/o t3 pr12c pr15c i/o u1 pr12b pr15b i/o u2 pr12a pr15a i/o u3 pr13d pr16d i/o v1 pr13c pr16b i/o v2 pr13b pr16a i/o v3 pr13a pr17d i/o w1 pr14d pr17a i/o-m3 v4 pr14c pr18d i/o w2 pr14b pr18b i/o w3 pr14a pr18a i/o y2 pr15d pr19d i/o w4 pr15a pr19a i/o-m2 y3 pr16d pr20d i/o aa1 pr16c pr20c i/o aa2 pr16b pr20b i/o y4 pr16a pr20a i/o aa3 pr17d pr21d i/o ab1 pr17c pr21c i/o ab2 pr17b pr21b i/o ab3 pr17a pr21a i/o ac1 pr18d pr22d i/o-m1 ac2 pr18c pr23d i/o ab4 pr18b pr23b i/o ac3 pr18a pr23a i/o ad2 pr19d pr24a i/o ad3 pr19c pr25c i/o ac4 pr19b pr25b i/o ae1 pr19a pr25a i/o ae2 pr20d pr26d i/o ae3 pr20c pr26c i/o ad4 pr20b pr26b i/o af1 pr20a pr26a i/o af2 pr21d pr27d i/o af3 pr21c pr27c i/o ag1 pr21b pr27b i/o ag2 pr21a pr27a i/o ag3 pr22d pr28d i/o af4 pr22c pr28c i/o ah1 pr22b pr28b i/o ah2 pr22a pr28a i/o-m0 ah3 pprgmn pprgmn prgm ag4 presetn presetn reset ah5 pdone pdone done aj4 pb22d pb28d i/o ak4 pb22c pb28c i/o al4 pb22b pb28b i/o ah6 pb22a pb28a i/o pin or3c/t80 pad or3t125 pad function pin information ( continued ) table 74. or3c/t80 and or3t125 432-pin ebga pinout
lucent technologies inc. 183 data sheet june 1999 orca series 3c and 3t fpgas aj5 pb21d pb27d i/o ak5 pb21c pb27c i/o al5 pb21b pb27b i/o aj6 pb21a pb27a i/o ak6 pb20d pb26d i/o al6 pb20c pb26c i/o ah8 pb20b pb26b i/o aj7 pb20a pb26a i/o ak7 pb19d pb25d i/o al7 pb19c pb25c i/o ah9 pb19b pb25b i/o aj8 pb19a pb25a i/o ak8 pb18d pb24d i/o aj9 pb18c pb24c i/o ah10 pb18b pb24b i/o ak9 pb18a pb24a i/o- init al9 pb17d pb23d i/o aj10 pb17c pb23c i/o ak10 pb17b pb23a i/o al10 pb17a pb22a i/o aj11 pb16d pb21d i/o ah12 pb16c pb21a i/o ak11 pb16b pb20d i/o al11 pb16a pb20a i/o- ldc aj12 pb15d pb19d i/o ah13 pb15b pb19b i/o ak12 pb15a pb19a i/o aj13 pb14d pb18d i/o ak13 pb14c pb18b i/o ah14 pb14b pb18a i/o-hdc al13 pb14a pb17d i/o aj14 pb13d pb17b i/o ak14 pb13c pb17a i/o al14 pb13b pb16d i/o aj15 pb13a pb16a i/o ak15 pb12d pb15d i/o al15 pb12c pb15c i/o ak16 pb12b pb15b i/o ah16 peckb peckb i-eckb aj16 pb11d pb14d i/o al17 pb11c pb14c i/o ak17 pb11b pb14b i/o aj17 pb11a pb14a i/o al18 pb10d pb13d i/o ak18 pb10c pb13b i/o aj18 pb10b pb13a i/o pin or3c/t80 pad or3t125 pad function al19 pb10a pb12d i/o ah18 pb9d pb12a i/o ak19 pb9c pb11d i/o aj19 pb9b pb11b i/o ak20 pb9a pb11a i/o ah19 pb8d pb10d i/o aj20 pb8b pb10b i/o al21 pb8a pb10a i/o ak21 pb7d pb9d i/o ah20 pb7c pb9a i/o aj21 pb7b pb8d i/o al22 pb7a pb8a i/o ak22 pb6d pb7d i/o aj22 pb6c pb7a i/o al23 pb6b pb6d i/o ak23 pb6a pb6a i/o ah22 pb5d pb5d i/o aj23 pb5c pb5c i/o ak24 pb5b pb5b i/o aj24 pb5a pb5a i/o ah23 pb4d pb4d i/o-a17 al25 pb4c pb4c i/o ak25 pb4b pb4b i/o aj25 pb4a pb4a i/o ah24 pb3d pb3d i/o al26 pb3c pb3c i/o ak26 pb3b pb3b i/o aj26 pb3a pb3a i/o al27 pb2d pb2d i/o ak27 pb2c pb2c i/o aj27 pb2b pb2b i/o ah26 pb2a pb2a i/o al28 pb1d pb1d i/o ak28 pb1c pb1c i/o aj28 pb1b pb1b i/o ah27 pb1a pb1a i/o-a16 ag28 pcclk pcclk cclk ah29 pl22a pl28a i/o-a15 ah30 pl22b pl28b i/o ah31 pl22c pl28c i/o af28 pl22d pl28d i/o ag29 pl21a pl27a i/o-seckll ag30 pl21b pl27b i/o ag31 pl21c pl27c i/o af29 pl21d pl27d i/o af30 pl20a pl26a i/o pin or3c/t80 pad or3t125 pad function pin information ( continued ) table 74. or3c/t80 and or3t125 432-pin ebga pinout ( continued )
184 184 lucent technologies inc. data sheet june 1999 orca series 3c and 3t fpgas af31 pl20b pl26b i/o ad28 pl20c pl26c i/o ae29 pl20d pl26d i/o ae30 pl19a pl25a i/o ae31 pl19b pl25b i/o ac28 pl19c pl25c i/o ad29 pl19d pl24a i/o-a14 ad30 pl18a pl24d i/o ac29 pl18b pl23d i/o ab28 pl18c pl22c i/o ac30 pl18d pl22d i/o ac31 pl17a pl21a i/o ab29 pl17b pl21b i/o-a13 ab30 pl17c pl21c i/o ab31 pl17d pl21d i/o aa29 pl16a pl20a i/o y28 pl16b pl20b i/o aa30 pl16c pl20c i/o aa31 pl16d pl20d i/o-a12 y29 pl15a pl19a i/o-a11/ mpi_irq w28 pl15b pl19d i/o y30 pl15c pl18a i/o w29 pl14a pl18c i/o w30 pl14b pl18d i/o v28 pl14c pl17a i/o-a10/ mpi_bi w31 pl14d pl17c i/o v29 pl13a pl17d i/o v30 pl13b pl16a i/o v31 pl13c pl16c i/o u29 pl13d pl16d i/o-a9/ mpi_ack u30 pl12a pl15a i/o-a8/mpi_rw u31 pl12b pl15b i/o t30 pl12c pl15c i/o t28 pl12d pl15d i/o t29 pl11a pl14a i/o-a7/mpi_clk r31 pl11b pl14b i/o r30 pl11c pl14c i/o r29 peckl peckl i-eckl p31 pl10a pl13a i/o-a6 p30 pl10b pl13d i/o p29 pl10c pl12a i/o n31 pl10d pl12c i/o p28 pl9a pl12d i/o-a5 n30 pl9b pl11a i/o-a4 n29 pl9c pl11c i/o m30 pl9d pl11d i/o pin or3c/t80 pad or3t125 pad function n28 pl8a pl10a i/o m29 pl8c pl10c i/o l31 pl8d pl10d i/o l30 pl7a pl9a i/o-a3 m28 pl7b pl9b i/o l29 pl7c pl9c i/o k31 pl7d pl9d i/o k30 pl6a pl8a i/o-a2 k29 pl6b pl8b i/o j31 pl6c pl8c i/o j30 pl6d pl8d i/o k28 pl5a pl7d i/o-a1/ mpi_be1 j29 pl5b pl6b i/o h30 pl5c pl6c i/o h29 pl5d pl6d i/o j28 pl4a pl5d i/o g31 pl4b pl4b i/o g30 pl4c pl4c i/o g29 pl4d pl4d i/o h28 pl3a pl3a i/o f31 pl3b pl3b i/o f30 pl3c pl3c i/o f29 pl3d pl3d i/o e31 pl2a pl2a i/o e30 pl2b pl2b i/o e29 pl2c pl2c i/o f28 pl2d pl2d i/o-a0/ mpi_be0 d31 pl1a pl1a i/o d30 pl1b pl1b i/o d29 pl1c pl1c i/o e28 pl1d pl1d i/o d27 prd_data prd_data rd_data/tdo c28 pt1a pt1a i/o-tck b28 pt1b pt1b i/o a28 pt1c pt1c i/o d26 pt1d pt1d i/o c27 pt2a pt2a i/o b27 pt2b pt2b i/o a27 pt2c pt2c i/o c26 pt2d pt2d i/o b26 pt3a pt3a i/o a26 pt3b pt3b i/o d24 pt3c pt3c i/o c25 pt3d pt3d i/o b25 pt4a pt4a i/o-tms a25 pt4b pt4b i/o pin or3c/t80 pad or3t125 pad function pin information ( continued ) table 74. or3c/t80 and or3t125 432-pin ebga pinout ( continued )
lucent technologies inc. 185 data sheet june 1999 orca series 3c and 3t fpgas d23 pt4c pt4c i/o c24 pt4d pt4d i/o b24 pt5a pt5a i/o c23 pt5b pt5b i/o d22 pt5c pt5c i/o b23 pt5d pt5d i/o a23 pt6a pt6a i/o-tdi c22 pt6b pt6d i/o b22 pt6c pt7a i/o a22 pt6d pt7d i/o c21 pt7a pt8a i/o d20 pt7b pt8d i/o b21 pt7c pt9a i/o a21 pt7d pt9d i/o c20 pt8a pt10a i/o-dout d19 pt8c pt10d i/o b20 pt8d pt11a i/o c19 pt9a pt11c i/o b19 pt9b pt11d i/o d18 pt9c pt12a i/o-d0/din a19 pt9d pt12c i/o c18 pt10a pt12d i/o b18 pt10b pt13a i/o a18 pt10c pt13c i/o c17 pt10d pt13d i/o-d1 b17 pt11a pt14a i/o-d2 a17 pt11b pt14b i/o b16 pt11c pt14c i/o d16 pt11d pt14d i/o c16 pt12a pt15a i/o-d3 a15 pt12b pt15b i/o b15 pt12c pt15c i/o c15 peckt peckt i-eckt a14 pt13a pt16a i/o-d4 b14 pt13b pt16b i/o c14 pt13c pt16d i/o a13 pt13d pt17a i/o d14 pt14a pt17b i/o b13 pt14b pt17d i/o c13 pt14c pt18a i/o-d5 b12 pt14d pt18b i/o d13 pt15a pt18d i/o c12 pt15b pt19a i/o a11 pt15d pt19d i/o b11 pt16a pt20a i/o d12 pt16b pt20d i/o-d6 pin or3c/t80 pad or3t125 pad function c11 pt16c pt21a i/o a10 pt16d pt21d i/o b10 pt17a pt22d i/o c10 pt17b pt23b i/o a9 pt17c pt23c i/o b9 pt17d pt23d i/o d10 pt18a pt24a i/o c9 pt18b pt24b i/o b8 pt18c pt24c i/o c8 pt18d pt24d i/o-d7 d9 pt19a pt25a i/o a7 pt19b pt25b i/o b7 pt19c pt25c i/o c7 pt19d pt25d i/o d8 pt20a pt26a i/o a6 pt20b pt26b i/o b6 pt20c pt26c i/o c6 pt20d pt26d i/o a5 pt21a pt27a i/o-rdy/rclk/mpi_ale b5 pt21b pt27b i/o c5 pt21c pt27c i/o d6 pt21d pt27d i/o a4 pt22a pt28a i/o b4 pt22b pt28b i/o c4 pt22c pt28c i/o d5 pt22d pt28d i/o-seckur a12 v ss v ss v ss a16 v ss v ss v ss a2 v ss v ss v ss a20 v ss v ss v ss a24 v ss v ss v ss a29 v ss v ss v ss a3 v ss v ss v ss a30 v ss v ss v ss a8 v ss v ss v ss ad1 v ss v ss v ss ad31 v ss v ss v ss aj1 v ss v ss v ss aj2 v ss v ss v ss aj30 v ss v ss v ss aj31 v ss v ss v ss ak1 v ss v ss v ss ak29 v ss v ss v ss ak3 v ss v ss v ss ak31 v ss v ss v ss al12 v ss v ss v ss pin or3c/t80 pad or3t125 pad function pin information ( continued ) table 74. or3c/t80 and or3t125 432-pin ebga pinout ( continued )
186 186 lucent technologies inc. data sheet june 1999 orca series 3c and 3t fpgas al16 v ss v ss v ss al2 v ss v ss v ss al20 v ss v ss v ss al24 v ss v ss v ss al29 v ss v ss v ss al3 v ss v ss v ss al30 v ss v ss v ss al8 v ss v ss v ss b1 v ss v ss v ss b29 v ss v ss v ss b3 v ss v ss v ss b31 v ss v ss v ss c1 v ss v ss v ss c2 v ss v ss v ss c30 v ss v ss v ss c31 v ss v ss v ss h1 v ss v ss v ss h31 v ss v ss v ss m1 v ss v ss v ss m31 v ss v ss v ss t1 v ss v ss v ss t31 v ss v ss v ss y1 v ss v ss v ss y31 v ss v ss v ss a1 v dd v dd v dd a31 v dd v dd v dd aa28 v dd v dd v dd aa4 v dd v dd v dd ae28 v dd v dd v dd ae4 v dd v dd v dd ah11 v dd v dd v dd ah15 v dd v dd v dd pin or3c/t80 pad or3t125 pad function ah17 v dd v dd v dd ah21 v dd v dd v dd ah25 v dd v dd v dd ah28 v dd v dd v dd ah4 v dd v dd v dd ah7 v dd v dd v dd aj29 v dd v dd v dd aj3 v dd v dd v dd ak2 v dd v dd v dd ak30 v dd v dd v dd al1 v dd v dd v dd al31 v dd v dd v dd b2 v dd v dd v dd b30 v dd v dd v dd c29 v dd v dd v dd c3 v dd v dd v dd d11 v dd v dd v dd d15 v dd v dd v dd d17 v dd v dd v dd d21 v dd v dd v dd d25 v dd v dd v dd d28 v dd v dd v dd d4 v dd v dd v dd d7 v dd v dd v dd g28 v dd v dd v dd g4 v dd v dd v dd l28 v dd v dd v dd l4 v dd v dd v dd r28 v dd v dd v dd r4 v dd v dd v dd u28 v dd v dd v dd u4 v dd v dd v dd pin or3c/t80 pad or3t125 pad function pin information ( continued ) table 74. or3c/t80 and or3t125 432-pin ebga pinout ( continued )
lucent technologies inc. 187 data sheet june 1999 orca series 3c and 3t fpgas pin or3t125 pad function e4 prd_cfgn rd_cfg e3 pr1d i/o e2 pr1c i/o f5 pr1b i/o f4 pr1a i/o f3 pr2d i/o f2 pr2c i/o g5 pr2b i/o g4 pr2a i/o g3 pr3d i/o g2 pr3c i/o h5 pr3b i/o h4 pr3a i/o- wr h3 pr4d i/o h2 pr4c i/o j5 pr4b i/o j4 pr4a i/o j3 pr5d i/o j2 pr5c i/o j1 pr5b i/o k5 pr5a i/o k4 pr6d i/o k3 pr6c i/o k2 pr6b i/o k1 pr6a i/o l4 pr7d i/o l3 pr7c i/o l2 pr7b i/o l1 pr7a i/o- rd / mpi_strb m5 pr8d i/o m4 pr8c i/o m3 pr8b i/o m2 pr8a i/o m1 pr9d i/o n5 pr9c i/o n4 pr9b i/o n3 pr9a i/o- cs0 n2 pr10d i/o p4 pr10c i/o p5 pr10b i/o p3 pr10a i/o p2 pr11d i/o p1 pr11c i/o r4 pr11b i/o r5 pr11a i/o-cs1 r3 pr12d i/o r2 pr12c i/o r1 pr12b i/o t4 pr12a i/o t3 pr13d i/o t2 pr13c i/o u2 pr13b i/o u4 pr13a i/o u5 pr14d i/o u3 pr14c i/o u1 pr14b i/o v2 peckr i-eckr v4 pr15d i/o v5 pr15c i/o v3 pr15b i/o w2 pr15a i/o w3 pr16d i/o w4 pr16c i/o w5 pr16b i/o y2 pr16a i/o y3 pr17d i/o y4 pr17c i/o aa1 pr17b i/o aa2 pr17a i/o-m3 aa3 pr18d i/o aa4 pr18c i/o aa5 pr18b i/o ab1 pr18a i/o ab2 pr19d i/o ab3 pr19c i/o ab4 pr19b i/o ab5 pr19a i/o-m2 ac2 pr20d i/o ac3 pr20c i/o ac4 pr20b i/o ac5 pr20a i/o ad1 pr21d i/o ad2 pr21c i/o ad3 pr21b i/o ad4 pr21a i/o ad5 pr22d i/o-m1 ae1 pr22c i/o ae2 pr22b i/o ae3 pr22a i/o ae4 pr23d i/o af1 pr23c i/o af2 pr23b i/o pin or3t125 pad function pin information ( continued ) table 75. or3t125 600-pin ebga pinout
188 188 lucent technologies inc. data sheet june 1999 orca series 3c and 3t fpgas af3 pr23a i/o af4 pr24d i/o af5 pr24c i/o ag1 pr24b i/o ag2 pr24a i/o ag3 pr25d i/o ag4 pr25c i/o ag5 pr25b i/o ah2 pr25a i/o ah3 pr26d i/o ah4 pr26c i/o ah5 pr26b i/o aj2 pr26a i/o aj3 pr27d i/o aj4 pr27c i/o aj5 pr27b i/o ak2 pr27a i/o ak3 pr28d i/o ak4 pr28c i/o ak5 pr28b i/o al2 pr28a i/o-m0 al3 pprgmn prgm al4 presetn reset am5 pdone done an5 pb28d i/o ap5 pb28c i/o al6 i/o am6 pb28b i/o an6 pb28a i/o ap6 pb27d i/o al7 pb27c i/o am7 pb27b i/o an7 pb27a i/o ap7 pb26d i/o al8 pb26c i/o am8 pb26b i/o an8 pb26a i/o ap8 pb25d i/o al9 pb25c i/o am9 pb25b i/o an9 pb25a i/o ap9 pb24d i/o ar9 pb24c i/o al10 pb24b i/o am10 pb24a i/o- init an10 pb23d i/o pin or3t125 pad function ap10 pb23c i/o ar10 pb23b i/o am11 pb23a i/o an11 pb22d i/o ap11 pb22c i/o ar11 pb22b i/o al12 pb22a i/o am12 pb21d i/o an12 pb21c i/o ap12 pb21b i/o ar12 pb21a i/o al13 pb20d i/o am13 pb20c i/o an13 pb20b i/o ap13 pb20a i/o- ldc am14 pb19d i/o al14 pb19c i/o an14 pb19b i/o ap14 pb19a i/o ar14 pb18d i/o am15 pb18c i/o al15 pb18b i/o an15 pb18a i/o-hdc ap15 pb17d i/o ar15 pb17c i/o am16 pb17b i/o an16 pb17a i/o ap16 pb16d i/o ap17 pb16c i/o am17 pb16b i/o al17 pb16a i/o an17 pb15d i/o ar17 pb15c i/o ap18 pb15b i/o am18 peckb i-eckb al18 pb14d i/o an18 pb14c i/o ap19 pb14b i/o an19 pb14a i/o am19 pb13d i/o al19 pb13c i/o ap20 pb13b i/o an20 pb13a i/o am20 pb12d i/o ar21 pb12c i/o ap21 pb12b i/o pin or3t125 pad function pin information ( continued ) table 75. or3t125 600-pin ebga pinout ( continued )
lucent technologies inc. 189 data sheet june 1999 orca series 3c and 3t fpgas an21 pb12a i/o am21 pb11d i/o al21 pb11c i/o ar22 pb11b i/o ap22 pb11a i/o an22 pb10d i/o am22 pb10c i/o al22 pb10b i/o ap23 pb10a i/o an23 pb9d i/o am23 pb9c i/o al23 pb9b i/o ar24 pb9a i/o ap24 pb8d i/o an24 pb8c i/o am24 pb8b i/o al24 pb8a i/o ar25 pb7d i/o ap25 pb7c i/o an25 pb7b i/o am25 pb7a i/o ar26 pb6d i/o ap26 pb6c i/o an26 pb6b i/o am26 pb6a i/o al26 pb5d i/o ar27 pb5c i/o ap27 pb5b i/o an27 pb5a i/o am27 pb4d i/o-a17 al27 pb4c i/o ap28 pb4b i/o an28 pb4a i/o am28 pb3d i/o al28 pb3c i/o ap29 pb3b i/o an29 pb3a i/o am29 pb2d i/o al29 pb2c i/o ap30 pb2b i/o an30 pb2a i/o am30 pb1d i/o al30 pb1c i/o ap31 i/o an31 pb1b i/o am31 pb1a i/o-a16 pin or3t125 pad function al32 pcclk cclk al33 pl28a i/o-a15 al34 pl28b i/o ak31 pl28c i/o ak32 pl28d i/o ak33 i/o ak34 pl27a i/o-seckll aj31 pl27b i/o aj32 pl27c i/o aj33 pl27d i/o aj34 pl26a i/o ah31 pl26b i/o ah32 pl26c i/o ah33 pl26d i/o ah34 pl25a i/o ag31 pl25b i/o ag32 pl25c i/o ag33 pl25d i/o ag34 pl24a i/o-a14 ag35 pl24b i/o af31 pl24c i/o af32 pl24d i/o af33 pl23a i/o af34 pl23b i/o af35 pl23c i/o ae32 pl23d i/o ae33 pl22a i/o ae34 pl22b i/o ae35 pl22c i/o ad31 pl22d i/o ad32 pl21a i/o ad33 pl21b i/o-a13 ad34 pl21c i/o ad35 pl21d i/o ac31 pl20a i/o ac32 pl20b i/o ac33 pl20c i/o ac34 pl20d i/o-a12 ab32 pl19a i/o-a11/ mpi_irq ab31 pl19b i/o ab33 pl19c i/o ab34 pl19d i/o ab35 pl18a i/o aa32 pl18b i/o aa31 pl18c i/o aa33 pl18d i/o pin or3t125 pad function pin information ( continued ) table 75. or3t125 600-pin ebga pinout ( continued )
190 190 lucent technologies inc. data sheet june 1999 orca series 3c and 3t fpgas aa34 pl17a i/o-a10/ mpi_bi aa35 pl17b i/o y32 pl17c i/o y33 pl17d i/o y34 pl16a i/o w34 pl16b i/o w32 pl16c i/o w31 pl16d i/o-a9/ mpi_ack w33 pl15a i/o-a8/mpi_rw w35 pl15b i/o v34 pl15c i/o v32 pl15d i/o v31 pl14a i/o-a7/mpi_clk v33 pl14b i/o u34 pl14c i/o u33 peckl i-eckl u32 pl13a i/o-a6 u31 pl13b i/o t34 pl13c i/o t33 pl13d i/o t32 pl12a i/o r35 pl12b i/o r34 pl12c i/o r33 pl12d i/o-a5 r32 pl11a i/o-a4 r31 pl11b i/o p35 pl11c i/o p34 pl11d i/o p33 pl10a i/o p32 pl10b i/o p31 pl10c i/o n34 pl10d i/o n33 pl9a i/o-a3 n32 pl9b i/o n31 pl9c i/o m35 pl9d i/o m34 pl8a i/o-a2 m33 pl8b i/o m32 pl8c i/o m31 pl8d i/o l35 pl7a i/o l34 pl7b i/o l33 pl7c i/o l32 pl7d i/o-a1/ mpi_be1 k35 pl6a i/o k34 pl6b i/o pin or3t125 pad function k33 pl6c i/o k32 pl6d i/o k31 pl5a i/o j35 pl5b i/o j34 pl5c i/o j33 pl5d i/o j32 pl4a i/o j31 pl4b i/o h34 pl4c i/o h33 pl4d i/o h32 pl3a i/o h31 pl3b i/o g34 pl3c i/o g33 pl3d i/o g32 pl2a i/o g31 pl2b i/o f34 pl2c i/o f33 pl2d i/o-a0/ mpi_be0 f32 pl1a i/o f31 pl1b i/o e34 pl1c i/o e33 i/o e32 pl1d i/o d31 prd_data rd_data/tdo c31 pt1a i/o-tck b31 i/o e30 pt1b i/o d30 pt1c i/o c30 pt1d i/o b30 pt2a i/o e29 pt2b i/o d29 pt2c i/o c29 pt2d i/o b29 pt3a i/o e28 pt3b i/o d28 pt3c i/o c28 pt3d i/o b28 pt4a i/o-tms e27 pt4b i/o d27 pt4c i/o c27 pt4d i/o b27 pt5a i/o a27 pt5b i/o e26 pt5c i/o d26 pt5d i/o c26 pt6a i/o-tdi pin or3t125 pad function pin information ( continued ) table 75. or3t125 600-pin ebga pinout ( continued )
lucent technologies inc. 191 data sheet june 1999 orca series 3c and 3t fpgas b26 pt6b i/o a26 pt6c i/o d25 pt6d i/o c25 pt7a i/o b25 pt7b i/o a25 pt7c i/o e24 pt7d i/o d24 pt8a i/o c24 pt8b i/o b24 pt8c i/o a24 pt8d i/o e23 pt9a i/o d23 pt9b i/o c23 pt9c i/o b23 pt9d i/o d22 pt10a i/o-dout e22 pt10b i/o c22 pt10c i/o b22 pt10d i/o a22 pt11a i/o d21 pt11b i/o e21 pt11c i/o c21 pt11d i/o b21 pt12a i/o-d0/din a21 pt12b i/o d20 pt12c i/o c20 pt12d i/o b20 pt13a i/o b19 pt13b i/o d19 pt13c i/o e19 pt13d i/o-d1 c19 pt14a i/o-d2 a19 pt14b i/o b18 pt14c i/o d18 pt14d i/o e18 pt15a i/o-d3 c18 pt15b i/o b17 pt15c i/o c17 peckt i-eckt d17 pt16a i/o-d4 e17 pt16b i/o b16 pt16c i/o c16 pt16d i/o d16 pt17a i/o a15 pt17b i/o b15 pt17c i/o pin or3t125 pad function c15 pt17d i/o d15 pt18a i/o-d5 e15 pt18b i/o a14 pt18c i/o b14 pt18d i/o c14 pt19a i/o d14 pt19b i/o e14 pt19c i/o b13 pt19d i/o c13 pt20a i/o d13 pt20b i/o e13 pt20c i/o a12 pt20d i/o-d6 b12 pt21a i/o c12 pt21b i/o d12 pt21c i/o e12 pt21d i/o a11 pt22a i/o b11 pt22b i/o c11 pt22c i/o d11 pt22d i/o a10 pt23a i/o b10 pt23b i/o c10 pt23c i/o d10 pt23d i/o e10 pt24a i/o a9 pt24b i/o b9 pt24c i/o c9 pt24d i/o-d7 d9 pt25a i/o e9 pt25b i/o b8 pt25c i/o c8 pt25d i/o d8 pt26a i/o e8 pt26b i/o b7 pt26c i/o c7 pt26d i/o d7 pt27a i/o-rdy/rclk/mpi_ale e7 pt27b i/o b6 pt27c i/o c6 pt27d i/o d6 pt28a i/o e6 pt28b i/o b5 pt28c i/o c5 i/o d5 pt28d i/o-seckur pin or3t125 pad function pin information ( continued ) table 75. or3t125 600-pin ebga pinout ( continued )
192 192 lucent technologies inc. data sheet june 1999 orca series 3c and 3t fpgas a13 v ss v ss a16 v ss v ss a20 v ss v ss a23 v ss v ss a28 v ss v ss a29 v ss v ss a3 v ss v ss a32 v ss v ss a33 v ss v ss a4 v ss v ss a7 v ss v ss a8 v ss v ss ac1 v ss v ss ac35 v ss v ss ah1 v ss v ss ah35 v ss v ss aj1 v ss v ss aj35 v ss v ss am1 v ss v ss am2 v ss v ss am3 v ss v ss am33 v ss v ss am34 v ss v ss am35 v ss v ss an1 v ss v ss an2 v ss v ss an32 v ss v ss an34 v ss v ss an35 v ss v ss an4 v ss v ss ap3 v ss v ss ap32 v ss v ss ap33 v ss v ss ap4 v ss v ss ar13 v ss v ss ar16 v ss v ss ar20 v ss v ss ar23 v ss v ss ar28 v ss v ss ar29 v ss v ss ar3 v ss v ss ar32 v ss v ss ar33 v ss v ss ar4 v ss v ss ar7 v ss v ss ar8 v ss v ss pin or3t125 pad function b3 v ss v ss b32 v ss v ss b33 v ss v ss b4 v ss v ss c1 v ss v ss c2 v ss v ss c32 v ss v ss c34 v ss v ss c35 v ss v ss c4 v ss v ss d1 v ss v ss d2 v ss v ss d3 v ss v ss d33 v ss v ss d34 v ss v ss d35 v ss v ss g1 v ss v ss g35 v ss v ss h1 v ss v ss h35 v ss v ss n1 v ss v ss n35 v ss v ss t1 v ss v ss t35 v ss v ss y1 v ss v ss y35 v ss v ss a1 v dd v dd a17 v dd v dd a18 v dd v dd a2 v dd v dd a30 v dd v dd a31 v dd v dd a34 v dd v dd a35 v dd v dd a5 v dd v dd a6 v dd v dd ae31 v dd v dd ae5 v dd v dd ak1 v dd v dd ak35 v dd v dd al1 v dd v dd al11 v dd v dd al16 v dd v dd al20 v dd v dd al25 v dd v dd al31 v dd v dd pin or3t125 pad function pin information ( continued ) table 75. or3t125 600-pin ebga pinout ( continued )
lucent technologies inc. 193 data sheet june 1999 orca series 3c and 3t fpgas al35 v dd v dd al5 v dd v dd am32 v dd v dd am4 v dd v dd an3 v dd v dd an33 v dd v dd ap1 v dd v dd ap2 v dd v dd ap34 v dd v dd ap35 v dd v dd ar1 v dd v dd ar18 v dd v dd ar19 v dd v dd ar2 v dd v dd ar30 v dd v dd ar31 v dd v dd ar34 v dd v dd ar35 v dd v dd ar5 v dd v dd ar6 v dd v dd b1 v dd v dd b2 v dd v dd b34 v dd v dd b35 v dd v dd pin or3t125 pad function c3 v dd v dd c33 v dd v dd d32 v dd v dd d4 v dd v dd e1 v dd v dd e11 v dd v dd e16 v dd v dd e20 v dd v dd e25 v dd v dd e31 v dd v dd e35 v dd v dd e5 v dd v dd f1 v dd v dd f35 v dd v dd l31 v dd v dd l5 v dd v dd t31 v dd v dd t5 v dd v dd u35 v dd v dd v1 v dd v dd v35 v dd v dd w1 v dd v dd y31 v dd v dd y5 v dd v dd pin or3t125 pad function pin information ( continued ) table 75. or3t125 600-pin ebga pinout ( continued )
194 194 lucent technologies inc. data sheet june 1999 orca series 3c and 3t fpgas package thermal characteristics there are four thermal parameters that are in common use: q ja , y jc, q jc, and q jb . it should be noted that all the parameters are affected, to varying degrees, by package design (including paddle size) and choice of materials, the amount of copper in the test board or system board, and system airflow. the data base containing the thermal values for all of lucent technologies ic packages is currently being updated to conform to modern jedec standards. thus, table 76 contains the currently available thermal specifications for lucent technologies fpga pack- ages mounted on both jedec and non-jedec test boards. the thermal values for the newer package types correspond to those packages mounted on a jedec four-layer board. the values for the older pack- ages, however, correspond to those packages mounted on a non-jedec, single-layer, sparse copper board (see note 2). it should also be noted that the values for the older packages are considered conservative. q ja this is the thermal resistance from junction to ambient (a.k.a. theta-ja, r-theta, etc.). where t j is the junction temperature, t a is the ambient air temperature, and q is the chip power. experimentally, q ja is determined when a special ther- mal test die is assembled into the package of interest, and the part is mounted on the thermal test board. the diodes on the test chip are separately calibrated in an oven. the package/board is placed either in a jedec natural convection box or in the wind tunnel, the latter for forced convection measurements. a controlled amount of power (q) is dissipated in the test chips heater resistor, the chips temperature (t j ) is deter- mined by the forward drop on the diodes, and the ambi- ent temperature (t a ) is noted. note that q ja is expressed in units of c/watt. y jc this jedec designated parameter correlates the junc- tion temperature to the case temperature. it is generally used to infer the junction temperature while the device is operating in the system. it is not considered a true thermal resistance, and it is defined by: where t c is the case temperature at top dead center, t j is the junction temperature, and q is the chip power. during the q ja measurements described above, besides the other parameters measured, an additional temperature reading, t c , is made with a thermocouple attached at top-dead-center of the case. y jc is also expressed in units of c/watt. q jc this is the thermal resistance from junction to case. it is most often used when attaching a heat sink to the top of the package. it is defined by: the parameters in this equation have been defined above. however, the measurements are performed with the case of the part pressed against a water-cooled heat sink so as to draw most of the heat generated by the chip out the top of the package. it is this difference in the measurement process that differentiates q jc from y jc. q jc is a true thermal resistance and is expressed in units of c/watt. q jb this is the thermal resistance from junction to board (a.k.a. q jl ). it is defined by: where t b is the temperature of the board adjacent to a lead measured with a thermocouple. the other param- eters on the right-hand side have been defined above. this is considered a true thermal resistance, and the measurement is made with a water-cooled heat sink pressed against the board so as to draw most of the heat out of the leads. note that q jb is expressed in units of c/watt, and that this parameter and the way it is measured is still in jedec committee. q ja t j t a C q ------------------- - = y jc t j t c C q -------------------- = q jc t j t c C q -------------------- = q jb t j t b C q ------------------ =
lucent technologies inc. 195 data sheet june 1999 orca series 3c and 3t fpgas package thermal characteristics (continued) fpga maximum junction temperature once the power dissipated by the fpga has been determined (see the estimating power dissipation section), the maximum junction temperature of the fpga can be found. this is needed to determine if speed derating of the device from the 85 c junction temperature used in all of the delay tables is needed. using the maximum ambient temperature, t amax , and the power dissipated by the device, q (expressed in c), the maximum junction tempera- ture is approximated by: t jmax = t amax + (q ? q ja ) table 76 lists the plastic package thermal characteristics for the orca series fpgas. table 76. plastic package thermal characteristics for the orca series 1 1. mounted on 4-layer jedec standard test board with two power/ground planes. 2. with thermal balls connected to board ground plane. 3. without thermal balls connected to board ground plane. package q ja (c/w) t a = 70 c max t j = 125 c max @ 0 fpm (w) 0 fpm 200 fpm 500 fpm 208-pin sqfp 1 26.5 23.0 21.0 2.1 208-pin sqfp2 1 12.8 10.3 9.1 4.3 240-pin sqfp 1 25.5 22.5 21.0 2.2 240-pin sqfp2 1 13.0 10.0 9.0 4.2 256-pin pbga 1, 2 22.5 19.0 17.5 2.4 256-pin pbga 1, 3 26.0 22.0 20.5 2.1 352-pin pbga 1, 2 19.0 16.0 15.0 2.9 352-pin pbga 1, 3 25.5 22.0 20.5 2.1 432-pin ebga 1 11.0 8.5 7.5 5.0 600-pin ebga 1 11.0 8.5 7.5 5.5
196 196 lucent technologies inc. data sheet june 1999 orca series 3c and 3t fpgas package coplanarity the coplanarity limits of the orca series 3 packages are as follows. table 77. package coplanarity package parasitics the electrical performance of an ic package, such as signal quality and noise sensitivity, is directly affected by the package parasitics. table 78 lists eight parasitics associated with the orca packages. these parasitics represent the contributions of all components of a package, which include the bond wires, all internal package routing, and the external leads. four inductances in nh are listed: l sw and l sl, the self-inductance of the lead; and l mw and l ml , the mutual inductance to the nearest neighbor lead. these parameters are important in determining ground bounce noise and inductive crosstalk noise. three capacitances in pf are listed: c m , the mutual capaci- tance of the lead to the nearest neighbor lead; and c 1 and c 2 , the total capacitance of the lead to all other leads (all other leads are assumed to be grounded). these parameters are important in determining capaci- tive crosstalk and the capacitive loading effect of the lead. the lead resistance value, r w , is in m w . the parasitic values in table 78 are for the circuit model of bond wire and package lead parasitics. if the mutual capacitance value is not used in the designers model, then the value listed as mutual capacitance should be added to each of the c 1 and c 2 capacitors. package type coplanarity limit (mils) ebga 8.0 pbga 8.0 sqfp/sqfp2 4.0 3.15 table 78. package parasitics 5-3862(f).a figure 104. package parasitics package type l sw l mw r w c 1 c 2 c m l sl l ml 208-pin sqfp 4 2 200 1 1 1 710 46 208-pin sqfp2 4 2 200 1 1 1 69 46 240-pin sqfp 4 2 200 1 1 1 812 58 240-pin sqfp2 4 2 200 1 1 1 711 47 256-pin pbga 5 2 220 1 1 1 58 24 352-pin pbga 5 2 220 1.5 1.5 1.5 712 36 432-pin ebga 4 1.5 500 1 1 0.3 35.5 0.51 600-pin ebga 4 1.5 500 1 1 0.4 36 0.51 pad n board pad c m c 1 l sw r w l sl l mw c 2 c 1 l ml c 2 pad n + 1 l sw r w l sl
lucent technologies inc. 197 data sheet june 1999 orca series 3c and 3t fpgas package outline diagrams terms and definitions basic size (bsc): the basic size of a dimension is the size from which the limits for that dimension are derived by the application of the allowance and the tolerance. design size: the design size of a dimension is the actual size of the design, including an allowance for fit and tolerance. typical (typ): when specified after a dimension, this indicates the repeated design size if a tolerance is specified or repeated basic size if a tolerance is not specified. reference (ref): the reference dimension is an untoleranced dimension used for informational purposes only. it is a repeated dimension or one that can be derived from other values in the drawing. minimum (min) or maximum (max): indicates the minimum or maximum allowable size of a dimension.
198 lucent technologies inc. data sheet june 1999 orca series 3c and 3t fpgas package outline diagrams (continued) 208-pin sqfp dimensions are in millimeters. note: the dimensions in this outline diagram are intended for informational purposes only. for detailed schematics to assist your design efforts, please contact your lucent technologies sales representative. 156 105 30.60 0.20 157 208 1 52 53 104 28.00 0.20 28.00 0.20 30.60 0.20 pin #1 identifier zone 4.10 max 0.08 3.40 0.20 seating plane 0.25 min 0.50 typ detail b detail a 0.50/0.75 gage plane seating plane 1.30 ref 0.25 detail a detail b 0.17/0.27 0.10 m 0.090/0.200
lucent technologies inc. 199 data sheet june 1999 orca series 3c and 3t fpgas package outline diagrams (continued) 208-pin sqfp2 dimensions are in millimeters. detail c (sqfp2 chip-up) 5-3828(f).a 5-3828(f) chip chip bonded face up copper heat sink 0.50/0.75 gage plane seating plane 1.30 ref 0.25 detail a detail b 0.17/0.2 0.1 0 m 0.090/0.200 156 105 30.60 0.20 157 208 53 104 28.00 0.20 exposed heat sink appears on bottom surface: chip bonded face up. (see detail c.) 28.00 0.20 30.60 0.20 pin #1 identifier zone 21.0 ref 21.0 ref 4.10 max 0.08 3.40 0.20 seating plane 0.25 min 0.50 typ detail b detail a
200 lucent technologies inc. data sheet june 1999 orca series 3c and 3t fpgas package outline diagrams (continued) 240-pin sqfp dimensions are in millimeters. note: the dimensions in this outline diagram are intended for informational purposes only. for detailed schematics to assist y our design efforts, please contact your lucent technologies sales representative. 0.50/0.75 gage plane seating plane 1.30 ref 0.25 detail a detail b 0.17/0.27 0.10 m 0.090/0.200 180 121 181 240 34.60 0.20 1 32.00 0.20 60 61 120 pin #1 identifier zone 32.00 0.20 34.60 0.20 0.08 3.40 0.20 s eating pla ne 0.25 min 0.50 typ detail a detail b 4.10 max
lucent technologies inc. 201 data sheet june 1999 orca series 3c and 3t fpgas package outline diagrams (continued) 240-pin sqfp2 dimensions are in millimeters. detail c (sqfp2 chip-up) 5-3825(f).a 0.50/0.75 gage plane seating plane 1.30 ref 0.25 detail a detail b 0.17/0.27 0.10 m 0.090/0.200 chip chip bonded face up copper heat sink 0.08 3.40 0.20 seating plane 0.25 min 0.50 typ detail a detail b 180 121 181 240 34.60 0.20 1 32.00 0.20 60 61 120 pin # 1 identi fier zone 32.00 0.20 34.60 0.20 exposed heat sink appears on bottom surface: chip bonded face up. (see detail c.) 24 .2 re f 24. 2 ref 4.10 max
202 lucent technologies inc. data sheet june 1999 orca series 3c and 3t fpgas package outline diagrams (continued) 256-pin pbga dimensions are in millimeters. 5-4406(f) note: although the 16 thermal enhancement balls are stated as an option, they are standard on the 256 fpga package. 0.36 0.04 1.17 0.05 2.13 0.19 seating plane solder ball 0.60 0.10 0.20 pwb mold compound 27.00 0.20 27.00 0.20 24.00 +0.70 C0.00 24.00 +0.70 C0.00 a1 ball identifier zone a b c d e f g h j k l m y n p r t u v w 12345678910 11 12 13 14 15 16 17 18 20 19 center array for thermal enhancement (optional) 19 spaces @ 1.27 = 24.13 a1 ball corner 19 spaces @ 1.27 = 24.13 0.75 0.15 (see note below)
lucent technologies inc. 203 data sheet june 1999 orca series 3c and 3t fpgas package outline diagrams (continued) 352-pin pbga dimensions are in millimeters. 5-4407(f) note: although the 36 thermal enhancement balls are stated as an option, they are standard on the 352 fpga package. 0.56 0.06 1.17 0.05 2.33 0.21 seating plane solder ball 0.60 0.10 0.20 pwb mold compound 35.00 +0.70 C0.00 30.00 a1 ball identifier zone af ae ad ac ab aa y w v u t r g 25 spaces @ 1.27 = 31.75 p n m l k j h 1 2 3 4 5 6 7 8 9 10 12 14 16 18 22 24 26 20 11 13 15 17 21 19 23 25 f e d c b a center array 25 spaces a1 ball 0.75 0.15 35.00 0.20 30.00 +0.70 C0.00 0.20 @ 1.27 = 31.75 for thermal enhancement (optional) corner (see note below)
204 lucent technologies inc. data sheet june 1999 orca series 3c and 3t fpgas package outline diagrams (continued) 432-pin ebga dimensions are in millimeters. 5-4409(f) 0.91 0.06 1.54 0.13 seating plane solder ball 0.63 0.07 0.20 40.00 0.10 40.00 a1 ball m d ag b f k h g e ad l t j n aj c y p ah ae ac aa w u r ak af ab v al a 19 30 26 5 28 24 22 23 25 7 20 31 29 15 21 18 327 11 17 4 6 810121416 2 913 1 30 spaces @ 1.27 = 38.10 30 spaces a1 ball 0.75 0.15 identifier zone 0.10 @ 1.27 = 38.10 corner
lucent technologies inc. 205 data sheet june 1999 orca series 3c and 3t fpgas package outline diagrams (continued) 600-pin ebga dimensions are in millimeters. 5-4408(f) 0.91 0.06 1.54 0.13 seating plane solder ball 0.63 0.07 0.20 45.00 0.10 45.00 a1 ball t d h al f k b p m l j ah r c e y n u an g ad v am aj ag ae ac aa w ap ak af ab ar a 19 30 26 28 24 32 22 20 18 4 6 81012 1416 234 52325 731 29 15 21 327 11 17 913 1 35 33 34 spaces @ 1.27 = 43.18 34 spaces a1 ball 0.75 0.15 identifier zone 0.10 @ 1.27 = 43.18 corner
206 lucent technologies inc. data sheet june 1999 orca series 3c and 3t fpgas ordering information or3c80, -4 speed grade, 240-pin power quad shrink flat package (sqfp2), commercial temperature table 79. voltage options table 80. temperature options table 81. package options table 82. orca series 3 package matrix key: c = commercial, i = industrial. table 83. speed grade options device voltage or3cxx 5.0 v or3txxx 3.3 v symbol description temperature (blank) commercial 0 c to 70 c i industrial C40 c to +85 c symbol description ba plastic ball grid array (pbga) bc enhanced ball grid array (ebga) ps power quad shrink flat package (sqfp2) s shrink quad flat package (sqfp) packages 208-pin eiaj sqfp 208-pin eiaj/sqfp2 240-pin eiaj sqfp 240-pin eiaj/sqfp2 256-pin pbga 352-pin pbga 432-pin ebga 600-pin ebga s208 ps208 s240 ps240 ba256 ba352 bc432 bc600 or3t20 cl ci ci ci or3t30 ci ci ci ci or3c/t55 ci ci ci ci or3c/t80 ci ci ci ci or3t125 ci ci cici ci device speed grade or3cxx -4, -5 or3txxx -5, -6, -7 or3c80-4 ps 240 device type speed grade package type number of pins temperature range example:
lucent technologies inc. 207 data sheet june 1999 orca series 3c and 3t fpgas index a absolute maximum ratings, 96 and-or-invert (aoi), 6 and-or-invert (aoi),1 (see also supplemental logic interconnect cell (slic), 1 architecture overview, 69 aswe, 9, 11, 1517, 23, 33, 48 b bidirectional buffers (bidis), 6, 19, 43, 83 (see also routingand slic) bit stream (see fpga configuration) bit stream error checking, 88 (see also fpga states of operation) boundary scan, 55 (see special function blocks) c clock control (clkcntrl), 50 (see also clock distribution network and special function blocks) clock distribution network, 48C51 clkcntrl, 50 expressclk, 48 inputs, 51 fast clock, 48, 51 global control signals, 48 in the pics expressclk, 50 system clock, 50 in the plc array fast clock, 49 system clock, 49 pfu clock sources, 48 selecting clock input pins, 51 system clock, 48 to the plc array fast clock, 50 system clock, 50 clock enable (ce), 9, 11, 17, 23, 31, 48 clock multiplication (see pcm) comparator (see lut operating modes) configuration (see fpga states of operation or fpga configuration) control inputs (see pics, inputs) d demultiplexing (see pics, input demultiplexing), 38 duty-cycle adjustment (see pcm) e electrical characteristics, 97, 98 error checking (see fpga configuration) expressclk, 1, 6, 31, 34, 37, 39, 41, 43, 4751, 7074, 7781 (see also clock distribution network and programmable clock manager) f fast clock, 4651, 54 (see clock distribution network) 5 v tolerant i/o 35 flexible input structure (fins) 1, 27, 32 (see also routing) fpga configuration, 8794 configuration frame format, 87 configuration modes, 89 asynchronous peripheral mode, 91 daisy-chaining, 95 master parallel mode, 89 master serial mode, 90 microprocessor interface (mpi) mode, 91 slave parallel mode, 94 slave serial mode, 94 data format, 86 data frame, 86 using orca foundry to generate ram data, 86 fpga states of operation configuration, 83 initialization, 82 other configuration options, 85 partial reconfiguration, 85 reconfiguration, 85 start-up, 84 i ieee standard, 1149.1 55, 59 initialization (see fpga states of operation) input/output buffers measurement conditions, 138 output buffer characteristics or3cxx, 139 or3txxx, 141 j jtag (see boundry scan)
208 208 lucent technologies inc. data sheet june 1999 orca series 3c and 3t fpgas index (continued) l look-up table (lut) operating modes, 1118 adder-subtractor submode, 15 counter submode, 15 equality comparators, 16 half-logic mode, 14 logic mode, 12 memory mode, 17 multiplier submode, 16 ripple mode, 14 lsr, 11, 17, 2324, 31, 48 m maximum ratings (see absolute maximum ratings) microprocessor interface (mpi), 6269 i960 system, 64 interface to fpga, 65 powerpc system, 63 setup and control registers, 66 multiplexing (see output multiplexing) multiplier (see lut operating modes) o orca foundry development system, 25 overview, 7 ordering information package matrix, 207 package options, 207 temperature options, 207 voltage options, 207 output (see pics) output multiplexing, 39 p package information, 200206 package matrix, 204 package outline diagrams, 200 208-pin sqfp2, 199 240-pin sqfp2, 202 256-pin pbga, 203 352-pin pbga, 204 432-pin ebga, 205 600-pin ebga, 206 terms and definitions, 200 pal , 1 (see also supplemental logic and interconnect cell (slic)) 1 pic routing (see routing) pin information 208-pin sqfp2 pinout, 151 240-pin sqfp2 pinout, 156 256-pin pbga pinout, 162 352-pin pbga pinout, 165 432-pin ebga pinout, 177 600-pin ebga pinout, 184 package compatibility, 152 pin descriptions 147, 151 power dissipation, 144 5 v tolerant i/o, 143 or3cxx, 144 or3txxx, 145 powerpc (see microprocessor interface) programmable clock manager (pcm), 6, 81 clock delay, 74 clock multiplication, 75 dll mode, 73 pcm cautions, 81 pcm detailed programming, 77 pcm operation, 76 pcm/fpga internal interface, 76 pll mode, 74 registers, 71 programmable function unit (pfu), 9 cintrol inputs, 11 operating modes, 11 softwired luts (swl), 12 twin-quad architecture, 1, 8, 14, 19 programmable input/output cells (pics), 3444 5 v tolerant i/o, 35 architecture, 43 control inputs, 11, 23 aswe, 11 ce, 11 clk, 11 gsrn, 11, 24 lsr, 11 sel, 11 input demultiplexing, 38 inputs, 36 output multiplexing, 39 outputs, 39 open-drain output option, 39 propagation delays, 39 overview, 32 pio, 34 pio logic, 41 pio options, 35 pio register control signals, 41 zero-hold input, 37 programmable logic cells (plcs), 933 architecture, 32 latches/flip-flops, 23, 24 pfu, 9 propagation delays (see pics, outputs) routing, 25 slic, 1922
lucent technologies inc. 209 data sheet june 1999 orca series 3c and 3t fpgas index (continued) r ram (see also fpga configuration), 85 dual-port, 3, 10, 17 single-port, 3, 10, 17 recommended operating conditions, 95 reconfiguration (see fpga states of operation) routing 3-statable bidirectional buffers, 24 bidi routing, 24, 27 clock (and global ce and lsr) routing, 30 configurable interconnect points (cips), 24 control signal and fast-carry routing, 27 flexible input structure (fins), 26 inter-plc routing resources, 28 interquad routing, 44 intra-plc routing resources, 2627 minimizing routing delay, 30 overview, 5 pfu output switching, 26 pic routing, 4143 pic interquad (mid) routing, 46 plc routing, 2632 programmable corner cell routing, 45 slic connectivity, 27 switching routing segments (xsw), 26 s sel, 8, 10, 22 softwired luts (swls),1, 6, 11, 12 (see also look-up table operating modes) special function blocks boundary scan, 60 boundary-scan cells, 59 boundary-scan timing, 60 microprocessor interface (mpi), 6168 programmable clock manager (pcm), 6980 single function blocks, 51 clock control (clkcntrl), 53 global 3-state control (ts_all), 52 global set/reset (gsrn), 52 internal oscillator, 52 readback logic, 51 start-up logic, 53 start-up (see fpga states of operation) stopclk, 1, 5, 53 (see also special function blocks) subtractor (see lut operating modes) supplemental logic and interconnect cell (slic), 1, 1821 system clock (see clock distribution network), 47 3-state, 34, 1718, 34, 38, 4546, 52, 56, 59, 82, 84 t timing characteristics asynchronous peripheral configuration mode, 132 boundry-scan timing, 119 clock timing, 119 derating, 98 description, 98 general configuration mode timing, 129, 130 master parallel configuration mode, 131 master serial configuration mode, 130 microprocessor interface configuration timing, 137 pfu timing, 100 pio timing, 108, 109, 110 plc timing, 107 programmable clock manager timing, 115 readback timing, 139 slave parallel configuration mode, 134 slave serial configuration mode, 133 slic timing, 107 tolerant i/o (see 5 v tolerant i/o), 34 ts_all, 52 twin-quad architecture (see pfu), 1 uz zero-hold inputs, 3436
lucent technologies inc. reserves the right to make changes to the product(s) or information contained herein without notice. no liability is assumed as a result of their use or application. no rights under any patent accompany the sale of any such product(s) or information. orca is a registered trademark of lucent technologies inc. foundry is a trademark of xilinx, inc. copyright ? 1999 lucent technologies inc. all rights reserved printed in u.s.a. june 1999 ds99-087fpga (replaces ds98-163fpga-01) for additional information, contact your microelectronics group account manager or the following: internet: http://www.lucent.com/micro , or for fpga information, http://www.lucent.com/orca e-mail: docmaster@micro.lucent.com n. america: microelectronics group, lucent technologies inc., 555 union boulevard, room 30l-15p-ba, allentown, pa 18103 1-800-372-2447 , fax 610-712-4106 (in canada: 1-800-553-2448 , fax 610-712-4106) asia pacific: microelectronics group, lucent technologies singapore pte. ltd., 77 science park drive, #03-18 cintech iii, singap ore 118256 tel. (65) 778 8833 , fax (65) 777 7495 china: microelectronics group, lucent technologies (china) co., ltd., a-f2, 23/f, zao fong universe building, 1800 zhong shan xi road shanghai 200233 p. r. china tel. (86) 21 6440 0468 , ext. 316 , fax (86) 21 6440 0652 japan: microelectronics group, lucent technologies japan ltd., 7-18, higashi-gotanda 2-chome, shinagawa-ku, tokyo 141, japan tel. (81) 3 5421 1600 , fax (81) 3 5421 1700 europe: data requests: microelectronics group dataline: tel. (44) 7000 582 368 , fax (44) 1189 328 148 technical inquiries: germany: (49) 89 95086 0 (munich), united kingdom: (44) 1344 865 900 (ascot), france: (33) 1 40 83 68 00 (paris), sweden: (46) 8 594 607 00 (stockholm), finland: (358) 9 4354 2800 (helsinki), italy: (39) 02 6608131 (milan), spain: (34) 1 807 1441 (madrid)

▲Up To Search▲

Price & Availability of OR3T55

	To Download OR3T55 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .